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209 条记录 (耗时 0.034 秒)

    Structure and method for thermally stressing or testing a semiconductor device
    81.
    发明授权
    Structure and method for thermally stressing or testing a semiconductor device 有权
    用于热应力或测试半导体器件的结构和方法

    公开(公告)号：US07375371B2

    公开(公告)日：2008-05-20

    申请号：US11307324

    申请日：2006-02-01

    申请人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    发明人： Giuseppe La Rosa ,  Kevin W. Kolvenbach ,  John Greg Massey ,  Ping-Chuan Wang ,  Kai Xiu

    IPC分类号： H01L23/58 ,  H01L29/10 ,  G01R31/02

    CPC分类号： G01R31/2856

    摘要： A structure is provided which includes at least one semiconductor device and a diffusion heater in a continuous active semiconductor area of a substrate. One or more semiconductor devices are provided in a first region of the active semiconductor area and a diffusion heater is disposed adjacent thereto which consists essentially of a semiconductor material included in the active semiconductor area. Conductive isolation between the first region and the diffusion heater is achieved through use of a separating gate. The separating gate overlies an intermediate region of the active semiconductor area between the first region and the diffusion heater and the separating gate is biasable to conductively isolate the first region from the diffusion heater.

    摘要翻译： 提供了一种在衬底的连续有源半导体区域中包括至少一个半导体器件和扩散加热器的结构。 一个或多个半导体器件设置在有源半导体区域的第一区域中，并且扩散加热器邻近设置，其主要由包含在有源半导体区域中的半导体材料组成。 通过使用分离栅极实现第一区域和扩散加热器之间的导电隔离。 分离栅极覆盖在第一区域和扩散加热器之间的有源半导体区域的中间区域，并且分离栅极可偏置以将第一区域与扩散加热器导电隔离。

    Detection of residual liner materials after polishing in damascene process
    82.
    发明授权
    Detection of residual liner materials after polishing in damascene process 失效
    在镶嵌工艺中抛光后残留衬垫材料的检测

    公开(公告)号：US07361584B2

    公开(公告)日：2008-04-22

    申请号：US10904329

    申请日：2004-11-04

    申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

    摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

    CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION
    84.
    发明申请
    CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION 失效
    用于检测电解过程中金属挤压的电容监测器

    公开(公告)号：US20060066314A1

    公开(公告)日：2006-03-30

    申请号：US10711641

    申请日：2004-09-29

    申请人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    发明人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    IPC分类号： G01R31/08

    CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

    摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。

    Noncontact electrical testing with optical techniques
    90.
    发明授权
    Noncontact electrical testing with optical techniques 失效
    用光学技术进行非接触式电气测试

    公开(公告)号：US08742782B2

    公开(公告)日：2014-06-03

    申请号：US13191555

    申请日：2011-07-27

    申请人： Xu Ouyang ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

    发明人： Xu Ouyang ,  Tso-Hui Ting ,  Ping-Chuan Wang ,  Yongchun Xin

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31728

    摘要： An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

    摘要翻译： 提供了芯片上测试结构的非接触电测试的片上技术。 片上光电二极管从泵浦光源接收泵浦光，其中片上光电二极管电连接到测试结构，并且被配置为产生用于测试结构的电力。 片上耦合单元接收来自探针光源的探测光，其中片上耦合单元光学连接到传输探针光的片上波导。 响应于测试结构的接收电压输出，片内开关打开，并且当没有从测试结构接收到电压输出时，片上开关保持闭合。 当由测试结构输出的电压打开时，片上开关通过探测灯。 当没有从测试结构接收到电压输出时，片内开关通过保持关闭来阻止探测光。