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公开(公告)号：US06535435B2
公开(公告)日：2003-03-18
申请号：US10012522
申请日：2001-12-12
IPC分类号： G11C700
CPC分类号： H01L27/0222 , G11C5/145 , G11C5/147 , G11C11/4074 , H01L27/10897
摘要： A reference voltage generation circuit is provided which includes a p-channel type MOSFET used as an input transistor to allow a sufficient current to flow through a differential amplifier even if the threshold voltages of MOSFETs used in the differential amplifier significantly increase. A push-pull conversion circuit is coupled to the differential amplifier and has a double end configuration to provide a sufficiently high level to drive a p-channel output buffer. This arrangement allows a stable operation at a sufficiently low power supply voltage even if the threshold voltages of the MOSFETs forming the differential amplifier are high. It also allows quick activation when the power is turned on and provides high stability.
摘要翻译： 提供了一种参考电压产生电路，其包括用作输入晶体管的p沟道型MOSFET，以允许足够的电流流过差分放大器，即使差分放大器中使用的MOSFET的阈值电压显着增加。 推挽转换电路耦合到差分放大器并且具有双端配置以提供足够高的电平来驱动p沟道输出缓冲器。 即使形成差分放大器的MOSFET的阈值电压高，这种布置允许在足够低的电源电压下的稳定操作。 它还允许在电源打开时快速启动并提供高稳定性。
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82.发明授权Semiconductor memory device having a long data retention time with the increase in leakage current suppressed 失效具有抑制了泄漏电流增加的数据保持时间长的半导体存储器件
公开(公告)号：US6157055A
公开(公告)日：2000-12-05
申请号：US185633
申请日：1998-11-04
IPC分类号： H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/94
CPC分类号： H01L27/10808 , H01L27/10873
摘要： In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.
摘要翻译： 在诸如DRAM的半导体存储器件中，在隔离绝缘膜（1.2）的与半导体衬底（1.1）相对的边缘部分上布置导电膜（1.11'），其间具有薄的绝缘膜。 该导电膜（1.11'）电连接到存储电容器的下电极（1.11）。 这种新颖的布置可以独立于冶金pn结的位置来控制电pn结的位置，从而实现了抑制泄漏电流增加的数据保持时间长的半导体存储器件。
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公开(公告)号：US5115289A
公开(公告)日：1992-05-19
申请号：US742196
申请日：1991-08-05
申请人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
发明人： Dai Hisamoto , Toru Kaga , Shinichiro Kimura , Masahiro Moniwa , Haruhiko Tanaka , Atsushi Hiraiwa , Eiji Takeda
IPC分类号： H01L21/336 , H01L21/339 , H01L21/762 , H01L21/8238 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/108 , H01L27/11 , H01L29/10 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L21/76264 , H01L21/8238 , H01L21/8248 , H01L21/8249 , H01L27/10808 , H01L27/10826 , H01L27/10852 , H01L27/10873 , H01L27/10879 , H01L27/1108 , H01L29/1062 , H01L29/42384 , H01L29/66772 , H01L29/66795 , H01L29/66954 , H01L29/78654 , H01L21/76278
摘要： A semiconductor device, such as an FET or a charge coupled device, is provided having a channel or a charge coupled portion formed in a thin semiconductor layer which is substantially perpendicular to the substrate. Necessary electrodes, such as the gate electrode, and necessary insulating layers can be added at the thin semiconductor layer, and can maintain the necessary amount of electric current by securing the height of the semiconductor layer. The structure has the advantage that it can have its plane size reduced. Further, the semiconductor memory device using the above semiconductor device is suitable to high integration and has excellent electric characteristics.
摘要翻译： 提供了诸如FET或电荷耦合器件的半导体器件，其具有形成在基本上垂直于衬底的薄半导体层中的沟道或电荷耦合部分。 可以在薄的半导体层添加必要的电极，例如栅电极和必要的绝缘层，并且可以通过确保半导体层的高度来保持必要的电流量。 该结构具有能够减小其平面尺寸的优点。 此外，使用上述半导体器件的半导体存储器件适合于高集成度并且具有优异的电特性。
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公开(公告)号：US4970564A
公开(公告)日：1990-11-13
申请号：US287881
申请日：1988-12-21
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10808
摘要： A semiconductor memory device having STC cells wherein major portions of active regions consisting of channel-forming portions are tilted at an angle of 45.degree. with respect to the word lines and the bit lines that meet at right angles with each other, enabling the storage capacity portions to be arranged very densely and sufficiently large capacities to be maintained with very small cell areas. In the semiconductor memory device, furthermore, the storage capacity portions are formed even on the bit lines. Therefore, the bit lines are shielded, the capacitance between the bit lines decreases, and the memory array noise decreases.
摘要翻译： 具有STC单元的半导体存储器件，其中由沟道形成部分组成的有源区的主要部分相对于彼此成直角相交的字线和位线以45°的角度倾斜，使得存储容量 部分布置得非常密集和足够大的容量保持非常小的单元格区域。 此外，在半导体存储器件中，即使在位线上形成存储容量部分。 因此，位线被屏蔽，位线之间的电容减小，并且存储器阵列噪声降低。
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85.发明授权
公开(公告)号：US4918502A
公开(公告)日：1990-04-17
申请号：US123235
申请日：1987-11-20
申请人： Toru Kaga , Shinichiro Kimura , Hideo Sunami
发明人： Toru Kaga , Shinichiro Kimura , Hideo Sunami
IPC分类号： H01L27/108
CPC分类号： H01L27/10829
摘要： The present invention relates to a highly packaged semiconductor memory, and more particularly to a memory cell having a trench capacitor for use in a CMOS memory. The present invention discloses a semiconductor memory employing memory cells each constructed of a trench type charge storage capacitor formed within a substrate, and a switching transistor; one electrode of the capacitor having a sheath-shaped structure which is electrically continuous with the Si substrate at a bottom of a groove and whose sideward periphery is covered with an insulator, the other electrode of the capacitor having a part which is buried inside the sheath electrode and another part which is electrically connected with an impurity diffused layer to function as a source region of the transistor. Further, a structure in which a voltage of 1/2 V.sub.cc can be applied to a plate electrode of a memory cell having a trench capacitor is disclosed.
摘要翻译： 本发明涉及高度封装的半导体存储器，更具体地说，涉及一种具有用于CMOS存储器的沟槽电容器的存储单元。 本发明公开了一种半导体存储器，其采用由形成在衬底内的沟槽型电荷存储电容器构成的存储单元和开关晶体管; 电容器的一个电极具有鞘状结构，其在沟槽的底部与Si衬底电连接，并且其侧面被绝缘体覆盖，电容器的另一个电极具有埋在护套内的部分 电极和与杂质扩散层电连接以用作晶体管的源极区的另一部分。 此外，公开了可以向具有沟槽电容器的存储单元的板电极施加1/2Vcc的电压的结构。
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公开(公告)号：US4873560A
公开(公告)日：1989-10-10
申请号：US155698
申请日：1988-02-16
申请人： Hideo Sunami , Shinichiro Kimura , Toru Kaga
发明人： Hideo Sunami , Shinichiro Kimura , Toru Kaga
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10841 , Y10S257/922
摘要： This invention relates to a very large scale dynamic random access memory, and discloses a memory cell having a reduced step on the device surface portion and being hardly affected by incident radioactive rays. In a semiconductor memory consisting of a deep hole bored in a semiconductor substrate, a capacitor formed on the sidewall portion at the lower half of the deep hole and a switching transistor formed immediately above the capacitor, at least the half of a word line constituting the gate of the switching transistor is buried in an elongated recess formed at the surface portion of the semiconductor substrate.
摘要翻译： 本发明涉及一种非常大规模的动态随机存取存储器，并且公开了一种在器件表面部分上具有减小的步长并且几乎不受入射放射线影响的存储单元。 在由在半导体衬底中钻出的深孔组成的半导体存储器中，形成在深孔下半部分的侧壁部分上的电容器和形成在电容器上方的开关晶体管，至少形成一条字线的一半构成 开关晶体管的栅极被埋在形成在半导体衬底的表面部分处的细长凹部中。
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公开(公告)号：US08472258B2
公开(公告)日：2013-06-25
申请号：US13269425
申请日：2011-10-07
申请人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
发明人： Digh Hisamoto , Kan Yasui , Tetsuya Ishimaru , Shinichiro Kimura , Daisuke Okada
CPC分类号： G11C16/0425 , G11C16/12 , G11C16/14 , G11C16/26 , G11C16/3454 , G11C16/3459
摘要： An operation scheme for operating stably a semiconductor nonvolatile memory device is provided.When hot-hole injection is conducted in the semiconductor nonvolatile memory device of a split gate structure, the hot-hole injection is verified using a crossing point that does not change with time. Thus, an erased state can be verified without being aware of any time-varying changes.Also, programming or programming/erasure is conducted by repeating pulse voltage or multi-step voltage application to a gate section multiple times.
摘要翻译： 提供一种稳定运行半导体非易失性存储器件的操作方案。 当在分裂栅极结构的半导体非易失性存储器件中进行热空穴注入时，使用不随时间变化的交叉点来验证热孔注入。 因此，可以验证擦除状态，而不知道任何时变变化。 此外，通过将多次脉冲电压或多级电压施加到栅极部分进行编程或编程/擦除。
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公开(公告)号：US20120196411A1
公开(公告)日：2012-08-02
申请号：US13363268
申请日：2012-01-31
申请人： Ryuta TSUCHIYA , Shinichiro Kimura
发明人： Ryuta TSUCHIYA , Shinichiro Kimura
IPC分类号： H01L21/336
CPC分类号： H01L27/12 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1207
摘要： A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer) in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.
摘要翻译： 一种器件及其制造方法，其中，器件包括单晶半导体衬底和通过薄的掩埋绝缘膜与单晶半导体衬底分离并具有薄单晶半导体薄膜（SOI层）的SOI衬底 以相同的步骤形成SOI型MISFET和体型MISFET的良好扩散层区域，漏极区域，栅极绝缘膜和栅极电极。 本体型MISFET和SOI型MISFET形成在同一衬底上，从而通过制造SOI型MISFET和体型MISFET的制造步骤，可以减少电路板面积并简化工艺。
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89.发明授权公开(公告)号：US08143668B2
公开(公告)日：2012-03-27
申请号：US12481551
申请日：2009-06-09
IPC分类号： H01L29/78
CPC分类号： H01L21/823814 , H01L21/823828 , H01L21/823864
摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。
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公开(公告)号：US20120061774A1
公开(公告)日：2012-03-15
申请号：US13299471
申请日：2011-11-18
IPC分类号： H01L29/78
CPC分类号： H01L21/823814 , H01L21/823828 , H01L21/823864
摘要： Performance of a semiconductor device having a MIS transistor is improved. A semiconductor device includes: a pair of source/drain regions each formed by stacking a semiconductor layer on a main surface of a silicon substrate; a sidewall insulating film covering each sidewall of the source/drain regions; a gate electrode arranged so as to interpose a gate insulating film on the main surface of the silicon substrate at a position sandwiched by the sidewall insulating films in a plane; and extension regions formed to extend from a portion below and lateral to the gate electrode to a portion below and lateral to each of the source/drain regions, wherein a sidewall of the sidewall insulating film being adjacent to the gate insulating film and the gate electrode has an inclination of a forward tapered shape.
摘要翻译： 提高了具有MIS晶体管的半导体器件的性能。 半导体器件包括：一对源极/漏极区域，每个源极/漏极区域通过在硅衬底的主表面上层叠半导体层而形成; 覆盖源极/漏极区域的每个侧壁的侧壁绝缘膜; 栅电极，被布置成在平面内被所述侧壁绝缘膜夹持的位置处在所述硅衬底的主表面上插入栅极绝缘膜; 以及延伸区域，其形成为从栅极电极下方和横向的部分延伸到每个源极/漏极区域的下方和侧面的部分，其中侧壁绝缘膜的侧壁与栅极绝缘膜和栅极电极相邻 具有向前锥形的倾斜。
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