公开(公告)号：US20140054666A1

公开(公告)日：2014-02-27

申请号：US13592086

申请日：2012-08-22

申请人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

发明人： Haitao Liu ,  Akira Goda ,  Chandra Mouli ,  Krishna K. Parat

IPC分类号： H01L29/788

CPC分类号： H01L29/408 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include a memory cell string having a body having a channel extending therein and in contact with a source/drain, a select gate adjacent to the body, a plurality of access lines adjacent to the body, and a dielectric in a portion of the body between the source/drain and a level corresponding to an end of the plurality of access lines most adjacent to the select gate. The dielectric in the portion of the body does not extend along an entire length of the body. Other embodiments are described and claimed.

摘要翻译： 一些实施例包括具有主体的存储单元串，该主体具有在其中延伸并与源极/漏极接触的通道，与主体相邻的选择栅极，与主体相邻的多个访问线，以及在该部分中的电介质 源极/漏极与对应于与选择栅极最相邻的多条访问线路的端部相对应的电平。 身体部分中的电介质不会沿着身体的整个长度延伸。 描述和要求保护其他实施例。

公开(公告)号：US08493790B2

公开(公告)日：2013-07-23

申请号：US13308020

申请日：2011-11-30

申请人： Akira Goda ,  Seiichi Aritome

发明人： Akira Goda ,  Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers and bit line drivers, and no nodes of the circuitry are biased at zero volts.

摘要翻译： 公开了编程，读取和擦除存储器单元的方法。 在至少一个实施例中，存储器中的程序，感测和擦除操作是通过反向偏置操作进行的，例如改进串驱动器和位线驱动器中的高电压器件隔离和截止，并且电路的任何节点都不偏 零伏。

公开(公告)号：US08441860B2

公开(公告)日：2013-05-14

申请号：US13366557

申请日：2012-02-06

申请人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

发明人： Akira Goda ,  Taehoon Kim ,  Doyle Rivers ,  Roger Porter

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C5/145 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C2211/5621

摘要： Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.

摘要翻译： 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。

公开(公告)号：US08378412B2

公开(公告)日：2013-02-19

申请号：US12903264

申请日：2010-10-13

申请人： Akira Goda

发明人： Akira Goda

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/7889 ,  H01L29/7926

摘要： Memory arrays and their formation are disclosed. One such memory array has a string of series-coupled memory cells with a substantially vertical portion. A distance between adjacent memory cells at one end of the substantially vertical portion is greater than a distance between adjacent memory cells at an opposing end of the substantially vertical portion. For other embodiments, thicknesses of respective control gates of the memory cells and/or thicknesses of the dielectrics between successively adjacent control gates may increase as the distances of the respective control gates/dielectrics from the opposing end of the substantially vertical portion increase.

公开(公告)号：US20120236640A1

公开(公告)日：2012-09-20

申请号：US13486028

申请日：2012-06-01

申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

摘要： A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

摘要翻译： 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中所述子集小于所述串的所述多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

公开(公告)号：US20120188825A1

公开(公告)日：2012-07-26

申请号：US13011223

申请日：2011-01-21

申请人： Akira Goda

发明人： Akira Goda

IPC分类号： G11C16/04 ,  H01L29/78

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/11556

摘要： Memory devices, memory cell strings and methods of operating memory devices are shown. Configurations described include directly coupling an elongated body region to a source line. Configurations and methods shown should provide a reliable bias to a body region for memory operations such as erasing.

摘要翻译： 显示了存储器件，存储器单元串和操作存储器件的方法。 所描述的配置包括将细长体区直接耦合到源线。 显示的配置和方法应为存储器操作（如擦除）提供可靠的身体区域偏置。

公开(公告)号：US08228735B2

公开(公告)日：2012-07-24

申请号：US12707162

申请日：2010-02-17

申请人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

发明人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

摘要翻译： 记忆及其记忆阵列被公开。 一个这样的存储器阵列具有一串串联耦合的存储器单元，串联耦合到串联耦合存储器单元串的第一端的非可编程选择栅极，以及串联耦合到第二端的可编程选择栅极 串联的存储单元串。

公开(公告)号：US20120182797A1

公开(公告)日：2012-07-19

申请号：US13009540

申请日：2011-01-19

申请人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

发明人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

公开(公告)号：US08203876B2

公开(公告)日：2012-06-19

申请号：US12628522

申请日：2009-12-01

申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

摘要： Methods for programming and memory devices are disclosed. One such method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

摘要翻译： 公开了用于编程和存储器件的方法。 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中该子集小于该串的多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

公开(公告)号：US20120134215A1

公开(公告)日：2012-05-31

申请号：US12955448

申请日：2010-11-29

申请人： Akira Goda

发明人： Akira Goda

IPC分类号： G11C16/04 ,  H01L29/78

CPC分类号： G11C16/0483 ,  G11C7/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/78 ,  H01L29/7889 ,  H01L29/7926

摘要： Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

摘要翻译： 显示了存储器件和操作存储器件的方法。 所描述的配置包括具有细长n型体区并且具有p型体的选择栅的存储单元串。 所示的配置和方法可以为身体区域提供可靠的偏置，用于诸如擦除的存储器操作。