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    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES
    81.
    发明申请
    TECHNIQUES AND CONFIGURATIONS TO IMPART STRAIN TO INTEGRATED CIRCUIT DEVICES 审中-公开
    对集成电路设备进行驱动的技术和配置

    公开(公告)号：US20140103294A1

    公开(公告)日：2014-04-17

    申请号：US14106556

    申请日：2013-12-13

    申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    IPC分类号： H01L29/778 ,  H01L29/66

    CPC分类号： H01L29/7782 ,  B82Y10/00 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7848

    摘要： Embodiments of the present disclosure describe techniques and configurations to impart strain to integrated circuit devices such as horizontal field effect transistors. An integrated circuit device includes a semiconductor substrate, a quantum well channel coupled with the semiconductor substrate, a source structure coupled with the quantum well channel, a drain structure coupled with the quantum well channel and a strain-inducing film disposed on and in direct contact with material of the source structure and the drain structure to reduce resistance of the quantum well channel by imparting a tensile or compressive strain on the quantum well channel, wherein the quantum well channel is disposed between the strain-inducing film and the semiconductor substrate. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例描述了为诸如水平场效应晶体管等集成电路器件施加应变的技术和配置。 集成电路器件包括半导体衬底，与半导体衬底耦合的量子阱沟道，与量子阱沟道耦合的源极结构，与量子阱沟道耦合的漏极结构以及直接接触的应变诱导膜 其中源结构和漏极结构的材料通过在量子阱沟道上施加拉伸或压缩应变来降低量子阱沟道的电阻，其中量子阱沟道设置在应变诱导膜和半导体衬底之间。 可以描述和/或要求保护其他实施例。

    Quantum well transistors with remote counter doping
    82.
    发明授权
    Quantum well transistors with remote counter doping 有权
    具有远程反相掺杂的量子阱晶体管

    公开(公告)号：US08324661B2

    公开(公告)日：2012-12-04

    申请号：US12646589

    申请日：2009-12-23

    申请人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    发明人： Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Ravi Pillarisetty

    IPC分类号： H01L21/338 ,  H01L29/66

    CPC分类号： H01L29/66636 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7784

    摘要： A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.

    摘要翻译： 公开了一种量子阱器件及其制造方法。 在一个实施例中，量子阱结构包括覆盖在衬底上的量子阱区域和包括与量子阱区域的电荷载流子的导电性相反的导电性的掺杂剂的远程计数器掺杂。 远程计数器掺杂被结合在量子阱区域附近，用于与量子阱沟道交换移动载流子，从而减小截止状态的漏电流。 在另一个实施例中，量子阱器件包括量子阱结构，其包括远程反相掺杂，覆盖量子阱结构的一部分的栅极区域和与栅极区域相邻的源极和漏极区域。 量子阱器件还可以包括包含与量子阱沟道相同导电性的掺杂剂的远程δ掺杂。

    Epitaxial buffer layers for group III-N transistors on silicon substrates
    87.
    发明授权
    Epitaxial buffer layers for group III-N transistors on silicon substrates 有权
    在硅衬底上的III-N晶体管的外延缓冲层

    公开(公告)号：US09583574B2

    公开(公告)日：2017-02-28

    申请号：US13631514

    申请日：2012-09-28

    申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

    发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Niloy Mukherjee ,  Marko Radosavljevic ,  Robert S. Chau

    IPC分类号： H01L29/20 ,  H01L29/205 ,  H01L29/66 ,  H01L29/778 ,  H01L29/423

    CPC分类号： H01L29/7787 ,  H01L23/535 ,  H01L29/04 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66545

    摘要： Embodiments include epitaxial semiconductor stacks for reduced defect densities in III-N device layers grown over non-III-N substrates, such as silicon substrates. In embodiments, a metamorphic buffer includes an AlxIn1-xN layer lattice matched to an overlying GaN device layers to reduce thermal mismatch induced defects. Such crystalline epitaxial semiconductor stacks may be device layers for HEMT or LED fabrication, for example. System on Chip (SoC) solutions integrating an RFIC with a PMIC using a transistor technology based on group III-nitrides (III-N) capable of achieving high Ft and also sufficiently high breakdown voltage (BV) to implement high voltage and/or high power circuits may be provided on the semiconductor stacks in a first area of the silicon substrate while silicon-based CMOS circuitry is provided in a second area of the substrate.

    摘要翻译： 实施例包括用于在诸如硅衬底的非III-N衬底上生长的III-N器件层中的缺陷密度降低的外延半导体堆叠。 在实施例中，变质缓冲器包括与上覆GaN器件层匹配的Al x In 1-x N层晶格以减少热失配引起的缺陷。 这种结晶外延半导体叠层可以是用于例如HEMT或LED制造的器件层。 使用基于能够实现高Ft的III族氮化物（III-N）的晶体管技术并且还具有足够高的击穿电压（BV）来实现高电压和/或高电平的片上系统（SoC）解决方案集成RFIC与PMIC 电源电路可以设置在硅衬底的第一区域中的半导体堆叠上，而硅基CMOS电路设置在衬底的第二区域中。

    III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES
    88.
    发明申请
    III-N SEMICONDUCTOR-ON-SILICON STRUCTURES AND TECHNIQUES 审中-公开
    III-N硅半导体结构和技术

    公开(公告)号：US20140158976A1

    公开(公告)日：2014-06-12

    申请号：US13706473

    申请日：2012-12-06

    申请人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

    发明人： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Robert S. Chau

    IPC分类号： H01L21/36 ,  H01L29/06

    CPC分类号： H01L29/0684 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02642 ,  H01L21/02647 ,  H01L29/2003 ,  Y10S977/762

    摘要： III-N semiconductor-on-silicon integrated circuit structures and techniques are disclosed. In some cases, the structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer including a 3-D GaN layer on the nucleation layer and having a plurality of 3-D semiconductor structures, and a 2-D GaN layer on the 3-D GaN layer. The structure also may include a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer. Another structure includes a first semiconductor layer formed on a nucleation layer, the first semiconductor layer comprising a 2-D GaN layer on the nucleation layer, and a second semiconductor layer formed on or within the first semiconductor layer, wherein the second semiconductor layer includes AlGaN on the 2-D GaN layer and a GaN layer on the AlGaN layer.

    摘要翻译： 公开了III-N半导体硅集成电路结构和技术。 在一些情况下，该结构包括在成核层上形成的第一半导体层，第一半导体层在成核层上包含3-D GaN层并具有多个3-D半导体结构，以及2-D ​​GaN层 在3-D GaN层上。 该结构还可以包括形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括二维GaN层上的AlGaN和AlGaN层上的GaN层。 另一种结构包括形成在成核层上的第一半导体层，第一半导体层包括成核层上的2-D GaN层，以及形成在第一半导体层上或第一半导体层内的第二半导体层，其中第二半导体层包括AlGaN 在2-D GaN层和AlGaN层上的GaN层。