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    Memory device, memory system and autonomous driving apparatus
    81.
    发明授权
    Memory device, memory system and autonomous driving apparatus 有权

    公开(公告)号：US11264082B2

    公开(公告)日：2022-03-01

    申请号：US17024267

    申请日：2020-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

    IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408

    Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

    Three-dimensional semiconductor memory device
    82.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11233043B2

    公开(公告)日：2022-01-25

    申请号：US17002149

    申请日：2020-08-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Joo-Yong Park ,  Daeseok Byeon

    IPC: H01L25/18 ,  H01L23/00

    Abstract: A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.

    Integrated circuit device
    84.
    发明授权
    Integrated circuit device 有权

    公开(公告)号：US11114428B2

    公开(公告)日：2021-09-07

    申请号：US16806030

    申请日：2020-03-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Dongku Kang ,  Daeseok Byeon

    IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/18 ,  H01L23/00

    Abstract: An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.

    MEMORY DEVICE, MEMORY SYSTEM AND AUTONOMOUS DRIVING APPARATUS
    85.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM AND AUTONOMOUS DRIVING APPARATUS 有权

    公开(公告)号：US20210125659A1

    公开(公告)日：2021-04-29

    申请号：US17024267

    申请日：2020-09-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

    IPC: G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408

    Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

    FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS
    86.
    发明申请
    FLASH MEMORY DEVICE AND COMPUTING DEVICE INCLUDING FLASH MEMORY CELLS 有权

    公开(公告)号：US20210118488A1

    公开(公告)日：2021-04-22

    申请号：US17006990

    申请日：2020-08-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Hyunsurk Ryu

    IPC: G11C11/4093 ,  G11C11/408 ,  G11C11/4094 ,  G11C5/06 ,  G06N3/063

    Abstract: A flash memory device includes: first pads; second pads; third pads; a memory cell region including first metal pads and a memory cell array; and a peripheral circuit region including a second metal pads and vertically connected to the memory cell region by the first metal pads and the second metal pads directly. The peripheral circuit region includes a row decoder block; a buffer block storing a command and an address received from an external semiconductor chip through the first pads; a page buffer block connected to the memory cell array through bit lines, connected to the third pads through data lines, and exchanging data signals with the external semiconductor chip through the data lines and the third pads; and a control logic block receiving control signals from the external semiconductor chip through the second pads, and controlling the row decoder block and the page buffer block.

    MEMORY DEVICE
    87.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210091113A1

    公开(公告)日：2021-03-25

    申请号：US17023053

    申请日：2020-09-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chanho Kim ,  Daeseok Byeon ,  Dongku Kang

    IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  G11C8/14 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11526 ,  H01L23/528 ,  H01L27/11573

    Abstract: A memory device includes a peripheral circuit region comprising a first substrate, a plurality of metal layers over the first substrate, and a first metal pad, a cell region comprising a second substrate, a plurality of gate lines over the second substrate, a plurality of upper interconnection layers in the second substrate, and a second metal pad, wherein the cell region is vertically connected to the peripheral circuit region by the first metal pad and the second metal pad, a common source line between the second substrate and the plurality of gate lines, the common source line comprising a through hole, and a word line cut region extending across the plurality of gate lines and extending through the through hole of the common source line to be connected to a first upper interconnection layer from among the plurality of upper interconnection layers.

    Memory system and method of determining a failure in the memory system
    90.
    发明授权
    Memory system and method of determining a failure in the memory system 有权
    存储系统和确定存储器系统故障的方法

    公开(公告)号：US09412453B2

    公开(公告)日：2016-08-09

    申请号：US14536843

    申请日：2014-11-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoon-Hee Choi ,  Daeseok Byeon ,  Byunggil Jeon

    IPC: G11C16/00 ,  G11C16/08 ,  G11C8/08 ,  G11C8/18 ,  G11C29/02 ,  G11C29/50 ,  G11C16/34 ,  G11C29/12

    CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/18 ,  G11C16/3454 ,  G11C29/025 ,  G11C29/50012 ,  G11C2029/1202

    Abstract: An operating method of a memory system which includes a nonvolatile memory device including memory cells connected to a plurality of word lines, the operating method including pre-charging a selected one of the plurality of word lines; detecting a variation in a voltage or a current on the selected word line after the selected word line is floated; generating runtime failure information according to the detected variation; and determining a state of the selected word line or a state of a memory block including the selected word line, based on the runtime failure information.

    Abstract translation: 一种存储器系统的操作方法，包括：非易失性存储器件，其包括连接到多个字线的存储器单元，所述操作方法包括对所述多个字线中的所选择的一个字线进行预充电; 在所选择的字线浮动之后检测所选字线上的电压或电流的变化; 根据检测到的变化产生运行时故障信息; 以及基于所述运行时故障信息来确定所选字线的状态或包括所选字线的存储块的状态。

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