公开(公告)号：US06682979B2

公开(公告)日：2004-01-27

申请号：US09951152

申请日：2001-09-12

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L218234

CPC分类号： H01L21/823462 ,  H01L21/3145 ,  H01L21/31612

摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.

摘要翻译： 本发明包括在半导体衬底上形成氧化物区域的方法。 在至少一些基底上形成含氮层。 在形成含氮层之后，从衬底中的至少一些生长氧化物区域。 含氮层的氮分散在氧化物区域内。 本发明还包括形成与半导体衬底相关联的一对晶体管的方法。 提供基板。 限定衬底的第一区域，并且另外定义衬底的第二区域。 形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。 跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。 在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。 在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

公开(公告)号：US06660658B2

公开(公告)日：2003-12-09

申请号：US10205235

申请日：2002-07-26

申请人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

发明人： Gurtej S. Sandhu ,  John T. Moore ,  Neal R. Rueger

IPC分类号： H01L2131

CPC分类号： H01L21/02332 ,  H01L21/0234 ,  H01L21/265 ,  H01L21/28061 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： The invention encompasses a method of incorporating nitrogen into a silicon-oxide-containing layer. The silicon-oxide-containing layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer. The nitrogen is subsequently thermally annealed within the layer to bond at least some of the nitrogen to silicon within the layer. The invention also encompasses a method of forming a transistor. A gate oxide layer is formed over a semiconductive substrate. The gate oxide layer comprises silicon dioxide. The gate oxide layer is exposed to a nitrogen-containing plasma to introduce nitrogen into the layer, and the layer is maintained at less than or equal to 400° C. during the exposing. Subsequently, the nitrogen within the layer is thermally annealed to bond at least a majority of the nitrogen to silicon. At least one conductive layer is formed over the gate oxide layer. Source/drain regions are formed within the semiconductive substrate, and are gatedly connected to one another by the at least one conductive layer. The invention also encompasses transistor structures.

公开(公告)号：US06653184B2

公开(公告)日：2003-11-25

申请号：US09951307

申请日：2001-09-12

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L218238

CPC分类号： H01L21/823462 ,  H01L21/3145 ,  H01L21/31612

摘要： The invention encompasses a method of forming an oxide region over a semiconductor substrate. A nitrogen-containing layer is formed across at least some of the substrate. After the nitrogen-containing layer is formed, an oxide region is grown from at least some of the substrate. The nitrogen of the nitrogen-containing layer is dispersed within the oxide region. The invention also encompasses a method of forming a pair of transistors associated with a semiconductor substrate. A substrate is provided. A first region of the substrate is defined, and additionally a second region of the substrate is defined. A first oxide region is formed which covers at least some of the first region of the substrate, and which does not cover any of the second region of the substrate. A nitrogen-comprising layer is formed across at least some of the first oxide region and across at least some of the second region of the substrate. After the nitrogen-comprising layer is formed, a second oxide region is grown from the second region of the substrate. A first transistor gate is formed over the first oxide region, and a second transistor gate is formed over the second oxide region.

摘要翻译： 本发明包括在半导体衬底上形成氧化物区域的方法。 在至少一些基底上形成含氮层。 在形成含氮层之后，从衬底中的至少一些生长氧化物区域。 含氮层的氮分散在氧化物区域内。 本发明还包括形成与半导体衬底相关联的一对晶体管的方法。 提供基板。 限定衬底的第一区域，并且另外定义衬底的第二区域。 形成第一氧化物区域，其覆盖衬底的第一区域中的至少一些，并且不覆盖衬底的任何第二区域。 跨越第一氧化物区域中的至少一些并穿过衬底的至少一些第二区域形成含氮层。 在形成含氮层之后，从衬底的第二区域生长第二氧化物区域。 在第一氧化物区域上形成第一晶体管栅极，在第二氧化物区域上形成第二晶体管栅极。

公开(公告)号：US06638820B2

公开(公告)日：2003-10-28

申请号：US09779983

申请日：2001-02-08

申请人： John T. Moore

发明人： John T. Moore

IPC分类号： H01L218242

CPC分类号： H01L45/1658 ,  H01C17/075 ,  H01C17/288 ,  H01L27/24 ,  H01L29/685 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/942 ,  Y10S438/953

摘要： A method of precluding diffusion of a metal into adjacent chalcogenide material upon exposure to a quanta of actinic energy capable of causing diffusion of the metal into the chalcogenide material includes forming an actinic energy blocking material layer over the metal to a thickness of no greater than 500 Angstroms and subsequently exposing the actinic energy blocking material layer to said quanta of actinic energy. In one implementation, an homogenous actinic energy blocking material layer is formed over the metal and subsequently exposed to said quanta of actinic energy. A method of forming a non-volatile resistance variable device includes providing conductive electrode material over chalcogenide material having metal ions diffused therein. An actinic energy blocking material layer is formed on the conductive electrode material, the actinic energy blocking material layer being effective to shield actinic energy from reaching an interface of the conductive electrode material and the actinic energy blocking material to substantially preclude diffusion of the conductive electrode material into the chalcogenide material upon exposure to said actinic energy. A dielectric layer is formed on the actinic energy blocking material layer. The conductive electrode material is formed into a first electrode. A second electrode is provided proximate the chalcogenide material having the metal diffused therein. Non-volatile resistance variable devices manufacture by these and other methods are contemplated.

摘要翻译： 在暴露于能够使金属扩散到硫族化物材料中的光化能的量子时，排除金属扩散到相邻硫族化物材料中的方法包括在金属上形成光化能量阻挡材料层至厚度不大于500 然后将光化性能量阻挡材料层暴露于所述光化能量级。 在一个实施方案中，在金属上形成均匀的光化能阻挡材料层，随后暴露于所述光化能量级。 形成非易失性电阻可变器件的方法包括在其中扩散金属离子的硫族化物材料上提供导电电极材料。 在导电电极材料上形成光化学能量阻挡材料层，光化学能量阻挡材料层有效地屏蔽光化能到达导电电极材料和光化能阻挡材料的界面，从而基本排除导电电极材料的扩散 在暴露于所述光化能之后进入硫族化物材料。 在光化能阻挡材料层上形成介电层。 导电电极材料形成为第一电极。 靠近硫属化物材料设置第二电极，其中金属在其中扩散。 考虑通过这些和其他方法制造的非易失性电阻可变器件。

公开(公告)号：US06548405B2

公开(公告)日：2003-04-15

申请号：US10116385

申请日：2002-04-02

申请人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

发明人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

IPC分类号： H01L2144

CPC分类号： H01L21/28568 ,  C23C16/303 ,  C23C16/34 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/318 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

摘要： A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

公开(公告)号：US06462371B1

公开(公告)日：2002-10-08

申请号：US09229320

申请日：1999-01-13

申请人： Ronald A. Weimer ,  John T. Moore

发明人： Ronald A. Weimer ,  John T. Moore

IPC分类号： H01L27108

CPC分类号： H01L21/0276 ,  H01L21/02126 ,  H01L21/02219 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/3145 ,  H01L21/3146 ,  H01L21/3148 ,  H01L21/31604 ,  H01L21/31633 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10888 ,  H01L28/91 ,  Y10S257/90 ,  Y10S438/97

摘要： The present invention pertains to films comprising silicon and oxygen that are doped with carbon and the use of the films in integrated circuit technology, such as capacitor constructions, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors, DRAMs and semiconductive material assemblies.

摘要翻译： 本发明涉及掺杂有碳的硅和氧的膜以及集成电路技术中的膜的使用，例如电容器结构，DRAM构造，半导体材料组件，蚀刻工艺以及用于形成电容器，DRAM和半导体的方法 材料组件

公开(公告)号：US06429070B1

公开(公告)日：2002-08-06

申请号：US09651484

申请日：2000-08-30

申请人： Fernando Gonzalez ,  Kevin L. Beaman ,  John T. Moore ,  Ron Weimer

发明人： Fernando Gonzalez ,  Kevin L. Beaman ,  John T. Moore ,  Ron Weimer

IPC分类号： H01L218242

CPC分类号： H01L27/10858 ,  H01L27/1082 ,  H01L27/1203 ,  H01L28/91 ,  Y10S257/906

摘要： The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate including a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which includes a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

摘要翻译： 本发明包括形成DRAM单元的方法。 第一衬底被形成为包括通过绝缘材料彼此分离的第一DRAM子结构。 包括单晶材料的第二半导体衬底被结合到第一衬底。 在接合之后，第二DRAM子结构形成为与第一DRAM子结构电连接。 本发明还包括一种包括电容器结构的半导体结构和被限定为包围电容器结构的第一衬底。 半导体结构还包括结合到第一衬底和电容器结构上的单晶硅衬底。 另外，半导体结构包括在单晶硅衬底上的晶体管栅极，并且与电容器结构可操作地连接以限定DRAM单元。

公开(公告)号：US06365519B2

公开(公告)日：2002-04-02

申请号：US09836123

申请日：2001-04-16

申请人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

发明人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

IPC分类号： H01L2144

CPC分类号： H01L21/28568 ,  C23C16/303 ,  C23C16/34 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/318 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

摘要： A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

公开(公告)号：US06218293B1

公开(公告)日：2001-04-17

申请号：US09191294

申请日：1998-11-13

申请人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

发明人： Brenda D. Kraus ,  John T. Moore ,  Scott J. DeBoer

IPC分类号： H01L214763

CPC分类号： H01L21/28568 ,  C23C16/303 ,  C23C16/34 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/318 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832

摘要： A process used during the formation of a semiconductor device comprises the steps of placing a plurality of semiconductor wafers each having a surface into a chamber of a batch wafer processor such as a diffusion furnace. The wafers are heated to a temperature of between about 300° C. and about 550° C. With the wafers in the chamber, at least one of ammonia and hydrazine is introduced into the chamber, then a precursor comprising trimethylethylenediamine tris(dimethylamino)titanium and/or triethylaluminum is introduced into the chamber. In the chamber, a layer comprising aluminum nitride is simultaneously formed over the surface of each wafer. The inventive process allows for the formation of aluminum nitride or titanium aluminum nitride over the surface of a plurality of wafers simultaneously. A subsequent anneal of the aluminum nitride layer or the titanium aluminum nitride layer can be performed in situ.

摘要翻译： 在形成半导体器件期间使用的工艺包括以下步骤：将具有表面的多个半导体晶片放置在诸如扩散炉的批处理晶片处理器的腔室中。 将晶片加热至约300℃至约550℃之间的温度。在室中的晶片中，将氨和肼中的至少一种引入室中，然后将包含三甲基乙二胺三（二甲基氨基）钛 和/或三乙基铝被引入到室中。 在室中，在每个晶片的表面上同时形成包括氮化铝的层。 本发明的方法允许在多个晶片的表面上同时形成氮化铝或氮化铝钛。 氮化铝层或氮化铝钛层的随后的退火可以在原位进行。

公开(公告)号：US20110254075A1

公开(公告)日：2011-10-20

申请号：US13168902

申请日：2011-06-24

申请人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

发明人： Ronald A. Weimer ,  Don C. Powell ,  John T. Moore ,  Jeff A. McKee

IPC分类号： H01L29/788 ,  B82Y99/00

CPC分类号： H01L29/517 ,  H01L21/28273 ,  H01L29/511

摘要： A flash memory integrated circuit and a method for fabricating the same. A gate stack includes an initial oxide layer directly in contact with a silicon layer, defining an oxide-silicon interface therebetween. Additional oxide material is formed substantially uniformly along the oxide-silicon interface. Polysilicon grain boundaries at the interface are thereby passivated after etching. The interface can be is formed between a tunnel oxide and a floating gate, and passivating the grain boundaries reduces erase variability. Oxide in an upper storage dielectric layer is enhanced in the dilute steam oxidation. The thin oxide layers serve as diffusion paths to enhance uniform distribution of OH species across the buried interfaces being oxidized.

摘要翻译： 闪存集成电路及其制造方法。 栅极堆叠包括直接与硅层接触的初始氧化物层，在其间界定氧化物 - 硅界面。 另外的氧化物材料沿着氧化硅 - 硅界面基本均匀地形成。 因此在界面处的多晶硅晶界被蚀刻后钝化。 界面可以形成在隧道氧化物和浮动栅极之间，钝化晶界可以减少擦除变化。 在稀释蒸汽氧化中，上储存电介质层中的氧化物增强。 薄氧化物层用作扩散路径，以增强OH物质穿过被氧化的掩埋界面的均匀分布。