公开(公告)号：US20160042990A1

公开(公告)日：2016-02-11

申请号：US14922556

申请日：2015-10-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi KOEZUKA ,  Masami JINTYOU ,  Yukinori SHIMA ,  Takahiro IGUCHI

IPC: H01L21/768 ,  H01L27/12

CPC classification number: H01L21/76829 ,  G02F1/133345 ,  G02F1/136204 ,  G02F2001/136295 ,  G02F2201/50 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/3272 ,  H01L29/458 ,  H01L29/786 ,  H01L29/7869 ,  H01L51/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed.

Abstract translation: 为了提高包括诸如铜，铝，金或银的低电阻材料的半导体器件作为布线的可靠性。 提供一种半导体器件，包括电连接到半导体层的一对电极，该半导体层具有层叠结构，该层叠层结构包括与半导体层接触的第一保护层和含有低电阻材料的导电层并且接触 与第一保护层。 导电层的顶表面覆盖有用作处理导电层的掩模的第二保护层。 导电层的侧表面被第三保护层覆盖。 通过这种结构，抑制了含有低电阻材料的一对导电层的构成元素进入或扩散到半导体层中。

公开(公告)号：US20150263141A1

公开(公告)日：2015-09-17

申请号：US14645781

申请日：2015-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masami JINTYOU ,  Yukinori SHIMA

IPC: H01L29/66 ,  H01L21/385 ,  H01L21/441 ,  H01L21/02 ,  H01L29/24 ,  H01L29/49 ,  H01L21/4757 ,  H01L29/786 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/02472 ,  H01L21/02483 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/78621 ,  H01L29/7869

Abstract: Provided is a method for manufacturing a semiconductor device whose electric characteristics are prevented from being varied and whose reliability is improved. In the method, an insulating film is formed over an oxide semiconductor film, a buffer film is formed over the insulating film, oxygen is added to the buffer film and the insulating film, a conductive film is formed over the buffer film to which oxygen is added, and an impurity element is added to the oxide semiconductor film using the conductive film as a mask. An insulating film containing hydrogen and overlapping with the oxide semiconductor film may be formed after the impurity element is added to the oxide semiconductor film.

Abstract translation: 本发明提供一种半导体装置的制造方法，其防止电特性变化，提高其可靠性。 在该方法中，在氧化物半导体膜上形成绝缘膜，在绝缘膜上形成缓冲膜，向缓冲膜和绝缘膜添加氧，在氧气的缓冲膜上形成导电膜 并且使用导电膜作为掩模将杂质元素添加到氧化物半导体膜。 可以在将杂质元素添加到氧化物半导体膜之后形成含有氢并与氧化物半导体膜重叠的绝缘膜。

公开(公告)号：US20150084043A1

公开(公告)日：2015-03-26

申请号：US14486089

申请日：2014-09-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Noritaka ISHIHARA ,  Masashi OOTA ,  Masashi TSUBUKU ,  Masami JINTYOU ,  Yukinori SHIMA ,  Junichi KOEZUKA ,  Yasuharu HOSAKA ,  Shunpei YAMAZAKI

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/04 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/78693 ,  H01L29/78696

Abstract: Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a semiconductor device including an oxide semiconductor film are improved. The reliability of a semiconductor device including an oxide semiconductor film is improved. A semiconductor device including an oxide semiconductor layer; a metal oxide layer in contact with the oxide semiconductor layer, the metal oxide layer including an In-M oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf); and a conductive layer in contact with the metal oxide layer, the conductive layer including copper, aluminum, gold, or silver is provided. In the semiconductor device, y/(x+y) is greater than or equal to 0.75 and less than 1 where the atomic ratio of In to M included in the metal oxide layer is In:M=x:y.

Abstract translation: 在包括氧化物半导体膜的半导体器件中，氧化物半导体膜中的缺陷减少。 提高了包括氧化物半导体膜的半导体器件的电特性。 提高了包括氧化物半导体膜的半导体器件的可靠性。 一种包括氧化物半导体层的半导体器件; 与氧化物半导体层接触的金属氧化物层，所述金属氧化物层包含In-M氧化物（M为Ti，Ga，Y，Zr，La，Ce，Nd或Hf）; 和与金属氧化物层接触的导电层，提供包括铜，铝，金或银的导电层。 在半导体器件中，y /（x + y）大于或等于0.75且小于1，其中包含在金属氧化物层中的In与M的原子比为In：M = x：y。

公开(公告)号：US20140374908A1

公开(公告)日：2014-12-25

申请号：US14306862

申请日：2014-06-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichi Koezuka ,  Masami JINTYOU ,  Yukinori SHIMA ,  Takahiro IGUCHI

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76829 ,  G02F1/133345 ,  G02F1/136204 ,  G02F2001/136295 ,  G02F2201/50 ,  H01L21/7685 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/3272 ,  H01L29/458 ,  H01L29/786 ,  H01L29/7869 ,  H01L51/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: To improve the reliability of a semiconductor device including a low-resistance material such as copper, aluminum, gold, or silver as a wiring. Provided is a semiconductor device including a pair of electrodes electrically connected to a semiconductor layer which has a stacked-layer structure including a first protective layer in contact with the semiconductor layer and a conductive layer containing the low-resistance material and being over and in contact with the first protective layer. The top surface of the conductive layer is covered with a second protective layer functioning as a mask for processing the conductive layer. The side surface of the conductive layer is covered with a third protective layer. With this structure, entry or diffusion of the constituent element of the pair of conductive layers containing the low-resistance material into the semiconductor layer is suppressed.

Abstract translation: 为了提高包括诸如铜，铝，金或银的低电阻材料的半导体器件作为布线的可靠性。 提供一种半导体器件，其包括电连接到半导体层的一对电极，所述半导体层具有层叠结构，所述层叠结构包括与半导体层接触的第一保护层和包含低电阻材料的导电层并且接触 与第一保护层。 导电层的顶表面覆盖有用作处理导电层的掩模的第二保护层。 导电层的侧表面被第三保护层覆盖。 通过这种结构，抑制了含有低电阻材料的一对导电层的构成元素进入或扩散到半导体层中。

公开(公告)号：US20250169109A1

公开(公告)日：2025-05-22

申请号：US19028799

申请日：2025-01-17

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kenichi OKAZAKI ,  Masami JINTYOU ,  Yukinori SHIMA

IPC: H10D30/67 ,  H10D86/40 ,  H10D86/60 ,  H10D99/00

Abstract: A highly reliable semiconductor device with favorable electrical characteristics is provided. A semiconductor device includes a semiconductor layer, an insulating layer, a metal oxide layer, and a conductive layer. The semiconductor layer, the insulating layer, the metal oxide layer, and the conductive layer are stacked in this order. The semiconductor layer includes a first region, a pair of second regions, and a pair of third regions. The first region overlaps the metal oxide layer. The second regions sandwich the first region, overlap the insulating layer, and do not overlap the metal oxide layer. The third regions sandwich the first region and the pair of second regions, and do not overlap the insulating layer. The third region includes a portion having a lower resistance than the first region. The second region includes a portion having a higher resistance than the third region.

公开(公告)号：US20250151538A1

公开(公告)日：2025-05-08

申请号：US18833581

申请日：2023-02-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yasuharu HOSAKA ,  Yukinori SHIMA ,  Masami JINTYOU ,  Masataka NAKADA ,  Junichi KOEZUKA ,  Kenichi OKAZAKI

IPC: H10K59/124 ,  H10K59/12 ,  H10K59/121

Abstract: A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The first insulating layer has a first opening reaching the first conductive layer. The semiconductor layer is in contact with a top surface and a side surface of the first insulating layer and a top surface of the first conductive layer. The second conductive layer is provided over the semiconductor layer. The second conductive layer includes a second opening in a region overlapping with the first opening. The second insulating layer is provided over the semiconductor layer and the second conductive layer. The third conductive layer is provided over the second insulating layer. The first insulating layer has a stacked-layer structure of a third insulating layer and a fourth insulating layer over the third insulating layer. The fourth insulating layer includes a region having a film density higher than that of the third insulating layer.

公开(公告)号：US20250147370A1

公开(公告)日：2025-05-08

申请号：US19014390

申请日：2025-01-09

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yasuharu HOSAKA ,  Yukinori SHIMA ,  Kenichi OKAZAKI ,  Shunpei YAMAZAKI

IPC: G02F1/1368 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1345 ,  G02F1/1362 ,  H10D86/40 ,  H10D86/60

Abstract: The display device includes a first substrate provided with a driver circuit region that is located outside and adjacent to a pixel region and includes at least one second transistor which supplies a signal to the first transistor in each of the pixels in the pixel region, a second substrate facing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first interlayer insulating film including an inorganic insulating material over the first transistor and the second transistor, a second interlayer insulating film including an organic insulating material over the first interlayer insulating film, and a third interlayer insulating film including an inorganic insulating material over the second interlayer insulating film. The third interlayer insulating film is provided in part of an upper region of the pixel region, and has an edge portion on an inner side than the driver circuit region.

公开(公告)号：US20240379856A1

公开(公告)日：2024-11-14

申请号：US18664558

申请日：2024-05-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Masami JINTYOU ,  Yasutaka NAKAZAWA ,  Yukinori SHIMA

IPC: H01L29/786 ,  H01L27/12

Abstract: The stability of steps of processing a wiring formed using copper or the like is increased. The concentration of impurities in a semiconductor film is reduced. Electrical characteristics of a semiconductor device are improved. A semiconductor device includes a semiconductor film, a pair of first protective films in contact with the semiconductor film, a pair of conductive films containing copper or the like in contact with the pair of first protective films, a pair of second protective films in contact with the pair of conductive films on the side opposite the pair of first protective films, a gate insulating film in contact with the semiconductor film, and a gate electrode overlapping with the semiconductor film with the gate insulating film therebetween. In a cross section, side surfaces of the pair of second protective films are located on the outer side of side surfaces of the pair of conductive films.

公开(公告)号：US20240266443A1

公开(公告)日：2024-08-08

申请号：US18612525

申请日：2024-03-21

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yasuharu HOSAKA ,  Yukinori SHIMA ,  Masataka NAKADA ,  Masami JINTYOU

IPC: H01L29/786 ,  G02F1/1368 ,  H01L21/426 ,  H01L27/12 ,  H01L29/04 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H10K50/115 ,  H10K59/12 ,  H10K59/40

CPC classification number: H01L29/7869 ,  H01L29/04 ,  H01L29/423 ,  H01L29/42384 ,  H01L29/49 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/78633 ,  H01L29/78648 ,  G02F1/1368 ,  H01L21/426 ,  H01L27/1225 ,  H10K50/115 ,  H10K59/12 ,  H10K59/40

Abstract: A semiconductor device that includes a transistor is provided. The transistor includes a first conductive film that functions as a first gate electrode, a first gate insulating film, a first oxide semiconductor film that includes a channel region, a second gate insulating film, and a second oxide semiconductor film and a second conductive film that function as a second gate electrode. The second oxide semiconductor film includes a region higher in carrier density than the first oxide semiconductor film. The second conductive film includes a region in contact with the first conductive film.

公开(公告)号：US20230378371A1

公开(公告)日：2023-11-23

申请号：US18364749

申请日：2023-08-03

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Junichi KOEZUKA ,  Kenichi OKAZAKI ,  Yukinori SHIMA ,  Shinpei MATSUDA ,  Haruyuki BABA ,  Ryunosuke HONDA

IPC: H01L29/786 ,  H01L29/778 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7786 ,  H01L29/78648 ,  H01L21/823412 ,  H01L21/02565 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/78696 ,  H01L29/24

Abstract: To improve field-effect mobility and reliability in a transistor including an oxide semiconductor film. A semiconductor device includes a transistor including an oxide semiconductor film. The transistor includes a region where the maximum value of field-effect mobility of the transistor at a gate voltage of higher than 0 V and lower than or equal to 10 V is larger than or equal to 40 and smaller than 150; a region where the threshold voltage is higher than or equal to minus 1 V and lower than or equal to 1 V; and a region where the S value is smaller than 0.3 V/decade.