公开(公告)号：US08502341B2

公开(公告)日：2013-08-06

申请号：US13021333

申请日：2011-02-04

申请人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

发明人： Chul Lee ,  Hyeong-Sun Hong ,  Deok-Sung Hwang ,  Jae-Man Yoon ,  Bong-Soo Kim

IPC分类号： H01L29/92

CPC分类号： H01L29/92

摘要： Provided is a trench-type capacitor. To form the capacitor, first and second active regions are disposed in a semiconductor substrate. Node patterns are disposed in the first active region. Each node pattern may have a conductive pattern and an insulating pattern, which are sequentially stacked. Impurity diffusion regions are disposed in the vicinity of the node patterns. Substrate connection patterns in electrical contact with the first and second active regions are disposed. Node connection patterns in electrical contact with the node patterns are disposed in the vicinity of the first and second active regions. In addition, a semiconductor device having the trench-type capacitor and a semiconductor module having the semiconductor device is provided.

摘要翻译： 提供了沟槽型电容器。 为了形成电容器，第一和第二有源区域设置在半导体衬底中。 节点图案设置在第一活动区域中。 每个节点图案可以具有顺序堆叠的导电图案和绝缘图案。 杂质扩散区域设置在节点图案附近。 设置与第一和第二有源区电接触的衬底连接图案。 与节点图案电接触的节点连接图案设置在第一和第二活动区域附近。 此外，提供具有沟槽型电容器的半导体器件和具有半导体器件的半导体模块。

公开(公告)号：US20120017517A1

公开(公告)日：2012-01-26

申请号：US13262549

申请日：2010-04-01

申请人： Chul Lee

发明人： Chul Lee

IPC分类号： E05B47/00 ,  E06B3/70 ,  E05B65/00

CPC分类号： E05F15/652 ,  E05B47/0012 ,  E05B83/363 ,  E05B2047/0023 ,  E05Y2201/22 ,  E05Y2201/232 ,  Y10T70/5155 ,  Y10T70/7062

摘要： An electrical door-locking device includes screws which are rotatable in a forwards and backwards direction, and are placed in line on one side of a door frame in the direction in which the electrical door main body slides; locking hooks located adjacent to the screws; and a sliding unit equipped with a rotatably-provided locking lever having a latch for latching onto the locking hooks when the electrical door main body is closed and is equipped with a locking-lever-pressing part for pressing the locking lever such that the latch of the locking lever unlatches from the locking hooks, and one end of which is rotatably linked to the screws and the other end of which is linked to the electrical door main body.

摘要翻译： 电气门锁装置包括可沿前后方向旋转的螺钉，并且沿着电门主体滑动的方向在门框的一侧成直线放置; 位于螺钉附近的锁定钩; 以及滑动单元，其具有可旋转地设置的锁定杆，当电门主体关闭时具有用于闩锁到锁定钩上的闩锁，并且配备有用于按压锁定杆的锁定杆按压部件， 锁定杆从锁定钩解锁，其一端可旋转地连接到螺钉，另一端连接到电动门主体。

公开(公告)号：US07700445B2

公开(公告)日：2010-04-20

申请号：US11804875

申请日：2007-05-21

申请人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

发明人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

IPC分类号： H01L21/336

CPC分类号： H01L21/823412

摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

摘要翻译： 为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。 在第二有源区上形成第一导电层以形成模具结构。 在模具结构之间形成掩模结构。 使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。 在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

公开(公告)号：US07667266B2

公开(公告)日：2010-02-23

申请号：US12116821

申请日：2008-05-07

申请人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim

发明人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.

摘要翻译： 公开了一种包括具有通道凹部的有源图案的半导体器件及其制造方法。 在一个实施例中，半导体器件包括有源图案，其包括第一有源区和介于第一有源区之间的第二有源区。 有源图案突出在半导体衬底的表面上方，并且包括在第二有源区上方和第一有源区之间的沟槽凹部。 器件隔离层围绕有源图案并且具有暴露凹陷的第二有源区域的侧壁的沟槽。 由通道凹部露出的第一有源区域的相对侧壁之间的距离大于槽的侧壁之间的距离。 栅极图案位于沟道凹部中并且沿着沟槽延伸。

公开(公告)号：US07579648B2

公开(公告)日：2009-08-25

申请号：US11183997

申请日：2005-07-19

申请人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

发明人： Jae-Man Yoon ,  Dong-Gun Park ,  Choong-Ho Lee ,  Chul Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/78696 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78642

摘要： A semiconductor device may include a tubular channel pattern vertically extending from a semiconductor substrate. A gate insulation layer may be provided on faces exposed through the channel pattern. A gate electrode may be provided on the gate insulation layer. The gate electrode may fill the channel pattern. A conductive region, which may serve as lower source/drain regions, may be formed at a surface portion of the semiconductor substrate. The conductive region may contact a lower portion of the channel pattern. A conductive pattern, which may serve as upper source/drain regions, may horizontally extend from an upper portion of the channel pattern.

摘要翻译： 半导体器件可以包括从半导体衬底垂直延伸的管状沟道图案。 可以在通过通道图案暴露的面上设置栅极绝缘层。 栅极电极可以设置在栅极绝缘层上。 栅电极可以填充沟道图案。 可以在半导体衬底的表面部分处形成可用作下部源极/漏极区域的导电区域。 导电区域可以接触通道图案的下部。 可以用作上部源极/漏极区域的导电图案可以从沟道图案的上部部分水平延伸。

公开(公告)号：US20080293203A1

公开(公告)日：2008-11-27

申请号：US12219984

申请日：2008-07-31

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

IPC分类号： H01L21/336

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

摘要翻译： 半导体器件可以包括具有连接在源极/漏极图案之间的源极/漏极区域和沟道鳍片的鳍结构。 栅极绝缘层可以设置在通道散热片上。 栅电极可以包括下栅极图案和上栅极图案。 下栅极图案可以在垂直方向上延伸并接触栅极绝缘层。 上栅极图案可以在基本上垂直于第一水平方向的第二水平方向上延伸。 上栅极图案可以连接到下栅极图案的上部。

公开(公告)号：US07420244B2

公开(公告)日：2008-09-02

申请号：US11183995

申请日：2005-07-19

申请人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

发明人： Jae-Man Yoon ,  Choong-Ho Lee ,  Chul Lee ,  Dong-Gun Park

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42384 ,  H01L29/66795

摘要： A semiconductor device may include a fin structure having source/drain regions and channel fins connected between source/drain patterns. A gate insulation layer may be provided on the channel fins. A gate electrode may include lower gate patterns and an upper gate pattern. The lower gate patterns may extend in a vertical direction and contact the gate insulation layer. The upper gate pattern may extend in a second horizontal direction substantially perpendicular to the first horizontal direction. The upper gate pattern may be connected to upper portions of the lower gate patterns.

公开(公告)号：US07410853B2

公开(公告)日：2008-08-12

申请号：US11431216

申请日：2006-05-10

申请人： Young-Joon Ahn ,  Choong-Ho Lee ,  Chul Lee

发明人： Young-Joon Ahn ,  Choong-Ho Lee ,  Chul Lee

IPC分类号： H01L21/336

CPC分类号： H01L21/3083 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/0665 ,  H01L29/0673 ,  Y10S977/938

摘要： In a method of forming a nanowire in a semiconductor device, a trench is formed by partially etching a bulk semiconductor substrate. An insulation layer pattern is formed on the substrate to fill up the trench. The insulation layer pattern covers a first region of the substrate where the nanowire is formed, and additionally covers a second region of the substrate connected to the first region. An opening is formed by etching an exposed portion of the substrate by the insulation layer pattern. A spacer is formed on sidewalls of the opening and the insulation layer pattern. The nanowire connected to the second region is formed by anisotropically etching a portion of the substrate exposed by the opening until a portion of the insulation layer pattern formed in the trench is exposed.

摘要翻译： 在半导体器件中形成纳米线的方法中，通过部分蚀刻体半导体衬底形成沟槽。 在衬底上形成绝缘层图案以填充沟槽。 绝缘层图案覆盖形成有纳米线的基板的第一区域，并且另外覆盖连接到第一区域的基板的第二区域。 通过用绝缘层图案蚀刻衬底的暴露部分形成开口。 在开口和绝缘层图案的侧壁上形成间隔物。 连接到第二区域的纳米线通过各向异性蚀刻由开口暴露的基板的一部分，直到形成在沟槽中的绝缘层图案的一部分露出而形成。

公开(公告)号：US07358142B2

公开(公告)日：2008-04-15

申请号：US11046623

申请日：2005-01-28

申请人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

发明人： Hee-Soo Kang ,  Chul Lee ,  Tae-Yong Kim ,  Dong-Gun Park ,  Young-Joon Ahn ,  Choong-Ho Lee ,  Sang-Yeon Han

IPC分类号： H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A device isolation film and an active region are formed on a semiconductor substrate, using a first mask pattern to expose only a formation region of the device isolation film. Only the device isolation film is selectively etched by using the first mask pattern and a second mask pattern as an etch mask, to form a fin only on a gate formation region, the second mask pattern to expose only a gate electrode formation region. A gate insulation layer is formed on both sidewalls of the fin and a gate electrode covering the first mask pattern and the gate insulation layer is formed. Source and drain regions are formed on the remaining portion of the active region where the gate electrode was not formed. Gate electrode separation becomes adequate and manufacturing costs can be reduced.

摘要翻译： 使用第一掩模图案在半导体衬底上形成器件隔离膜和有源区，仅暴露器件隔离膜的形成区域。 仅通过使用第一掩模图案和第二掩模图案作为蚀刻掩模来选择性地蚀刻器件隔离膜，仅在栅极形成区域形成鳍状物，第二掩模图案仅露出栅电极形成区域。 在翅片的两个侧壁上形成栅绝缘层，形成覆盖第一掩模图案的栅电极和栅极绝缘层。 源区和漏区形成在没有形成栅电极的有源区的剩余部分上。 栅电极分离变得足够，并且可以降低制造成本。

公开(公告)号：US07332386B2

公开(公告)日：2008-02-19

申请号：US11084922

申请日：2005-03-21

申请人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

发明人： Chul Lee ,  Min-Sang Kim ,  Dong-gun Park ,  Choong-ho Lee ,  Chang-woo Oh ,  Jae-man Yoon ,  Dong-won Kim ,  Jeong-dong Choe ,  Ming Li ,  Hye-jin Cho

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

CPC分类号： H01L29/785 ,  H01L21/26513 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/78624

摘要： A fin field effect transistor (FinFET) includes a substrate, a fin, a gate electrode, a gate insulation layer, and source and drain regions in the fin. The fin is on and extends laterally along and vertically away from the substrate. The gate electrode covers sides and a top of a portion of the fin. The gate insulation layer is between the gate electrode and the fin. The source region and the drain region in the fin and adjacent to opposite sides of the gate electrode. The source region of the fin has a different width than the drain region of the fin.

摘要翻译： 翅片场效应晶体管（FinFET）包括衬底，鳍，栅电极，栅极绝缘层以及鳍中的源极和漏极区。 翅片在基底上并沿着和垂直方向横向延伸。 栅电极覆盖翅片的一侧和顶部。 栅绝缘层位于栅电极和鳍之间。 翅片中的源极区域和漏极区域，并且与栅电极的相对侧相邻。 翅片的源极区域具有与鳍片的漏极区域不同的宽度。