公开(公告)号：US20070298599A1

公开(公告)日：2007-12-27

申请号：US11804875

申请日：2007-05-21

申请人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

发明人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

IPC分类号： H01L21/8232

CPC分类号： H01L21/823412

摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

摘要翻译： 为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。 在第二有源区上形成第一导电层以形成模具结构。 在模具结构之间形成掩模结构。 使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。 在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

公开(公告)号：US07700445B2

公开(公告)日：2010-04-20

申请号：US11804875

申请日：2007-05-21

申请人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

发明人： Se-Myeong Jang ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim ,  Hyun-Ju Sung ,  Hui-Jung Kim ,  Kyoung-Ho Jung

IPC分类号： H01L21/336

CPC分类号： H01L21/823412

摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.

摘要翻译： 为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。 在第二有源区上形成第一导电层以形成模具结构。 在模具结构之间形成掩模结构。 使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。 在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

公开(公告)号：US07667266B2

公开(公告)日：2010-02-23

申请号：US12116821

申请日：2008-05-07

申请人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim

发明人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Keun-Nam Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/00

CPC分类号： H01L21/823412 ,  H01L21/823456 ,  H01L29/66621 ,  H01L29/78

摘要： A semiconductor device including an active pattern having a channel recess portion, and a method of fabricating the same, are disclosed. In one embodiment, the semiconductor device includes an active pattern including first active regions and a second active region interposed between the first active regions. The active pattern protrudes above a surface of a semiconductor substrate and includes a channel recess portion above the second active region and between the first active regions. A device isolation layer surrounds the active pattern and has a groove exposing side walls of the recessed second active region. A distance between opposing side walls of the first active regions exposed by the channel recess portion is greater than a distance between side walls of the groove. A gate pattern is located in the channel recess portion and extends along the groove.

摘要翻译： 公开了一种包括具有通道凹部的有源图案的半导体器件及其制造方法。 在一个实施例中，半导体器件包括有源图案，其包括第一有源区和介于第一有源区之间的第二有源区。 有源图案突出在半导体衬底的表面上方，并且包括在第二有源区上方和第一有源区之间的沟槽凹部。 器件隔离层围绕有源图案并且具有暴露凹陷的第二有源区域的侧壁的沟槽。 由通道凹部露出的第一有源区域的相对侧壁之间的距离大于槽的侧壁之间的距离。 栅极图案位于沟道凹部中并且沿着沟槽延伸。

公开(公告)号：US07879703B2

公开(公告)日：2011-02-01

申请号：US12321335

申请日：2009-01-20

申请人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

发明人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC分类号： H01L21/425

CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

摘要翻译： 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

公开(公告)号：US20090186471A1

公开(公告)日：2009-07-23

申请号：US12321335

申请日：2009-01-20

申请人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

发明人： Kyoung-Ho Jung ,  Makoto Yoshida ,  Jae-Rok Kahng ,  Chul Lee ,  Joon-Seok Moon ,  Cheol-Kyu Lee ,  Sung-Il Cho

IPC分类号： H01L21/426 ,  H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/82385

摘要： A method of fabricating a semiconductor device for reducing a thermal burden on impurity regions of a peripheral circuit region includes preparing a substrate including a cell active region in a cell array region and peripheral active regions in a peripheral circuit region. A cell gate pattern and peripheral gate patterns may be formed on the cell active region and the peripheral active regions. First cell impurity regions may be formed in the cell active region. A first insulating layer and a sacrificial insulating layer may be formed to surround the cell gate pattern and the peripheral gate patterns. Cell conductive pads may be formed in the first insulating layer to electrically connect the first cell impurity regions. The sacrificial insulating layer may be removed adjacent to the peripheral gate patterns. First and second peripheral impurity regions may be sequentially formed in the peripheral active regions adjacent to the peripheral gate patterns.

摘要翻译： 制造用于减少外围电路区域的杂质区域的热负荷的半导体器件的方法包括制备包括单元阵列区域中的单元有源区和外围电路区中的外围有源区的基板。 单元栅极图案和外围栅极图案可以形成在单元有源区域和外围有源区域上。 可以在电池活性区域中形成第一电池杂质区域。 可以形成第一绝缘层和牺牲绝缘层以围绕电池栅极图案和外围栅极图案。 电池导电焊盘可以形成在第一绝缘层中以电连接第一电池杂质区。 牺牲绝缘层可以与外围栅极图案相邻地去除。 第一和第二外围杂质区域可以顺序地形成在与外围栅极图案相邻的外围有源区域中。

公开(公告)号：US09012982B2

公开(公告)日：2015-04-21

申请号：US12068179

申请日：2008-02-04

申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

IPC分类号： H01L29/66 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

公开(公告)号：US20080185641A1

公开(公告)日：2008-08-07

申请号：US12068179

申请日：2008-02-04

申请人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

发明人： Keun-Nam Kim ,  Makoto Yoshida ,  Chul Lee ,  Dong-Gun Park ,  Woun-Suck Yang

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

摘要： A recessed transistor and a method of manufacturing the same are provided. The recessed transistor may include a substrate, an active pin, a gate pattern and source and drain regions. The substrate may include an isolation layer that establishes an active region and a field region of the substrate. The substrate may include a recessed structure having an upper recess formed in the active region and a lower recess in communication with the upper recess. An active pin may be formed in a region between side surfaces of the isolation layer and the lower recess and an interface between the active region and the field region. The gate pattern may include a gate insulation layer formed on an inner surface of the recessed structure and a gate electrode formed on the gate insulation layer in the recessed structure. The source/drain regions may be formed adjacent to the active region and the gate electrode.

摘要翻译： 提供凹陷晶体管及其制造方法。 凹陷的晶体管可以包括衬底，有源引脚，栅极图案以及源极和漏极区域。 衬底可以包括建立衬底的有源区和场区的隔离层。 衬底可以包括具有形成在有源区域中的上凹部的凹陷结构和与上凹部连通的下凹部。 有源销可以形成在隔离层和下凹部的侧表面之间的区域中以及有源区域和场区域之间的界面。 栅极图案可以包括形成在凹陷结构的内表面上的栅极绝缘层和形成在凹陷结构中的栅极绝缘层上的栅电极。 源/漏区可以与有源区和栅电极相邻形成。

公开(公告)号：US20070134884A1

公开(公告)日：2007-06-14

申请号：US11488584

申请日：2006-07-18

申请人： Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

发明人： Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

IPC分类号： H01L21/76 ,  H01L29/00 ,  H01L21/4763

CPC分类号： H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7851

摘要： An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a semiconductor device includes: preparing a semiconductor substrate; and forming a plurality of active fins having major and minor axes and two-dimensionally arrayed on the semiconductor substrate in directions of the major and minor axes. A liner pattern is formed on lower sidewalls of the active fins. An isolation layer is formed on the semiconductor substrate having the liner pattern, and the isolation layer exposes top surfaces of the active fins and a part of the active fins' sidewalls substantially parallel to the major axis. Parallel gate lines are formed to cover the top surfaces and the exposed sidewalls of the active fins, cross over the active fins, and run on the isolation layer.

摘要翻译： 提供了限定有源散热片的隔离方法，制造使用其的半导体器件的方法以及由此制造的半导体器件。 制造半导体器件的方法包括：制备半导体衬底; 并且在所述主轴和短轴的方向上形成具有主轴和短轴的多个有源散热片，并且二维排列在所述半导体基板上。 衬垫图案形成在活动鳍片的下侧壁上。 在具有衬垫图案的半导体衬底上形成隔离层，并且隔离层暴露活性鳍片的顶表面和基本上平行于长轴的活性鳍片侧壁的一部分。 形成平行栅极线以覆盖活性鳍片的顶表面和暴露的侧壁，跨过活性鳍片并且在隔离层上运行。

公开(公告)号：US08791526B2

公开(公告)日：2014-07-29

申请号：US12891910

申请日：2010-09-28

申请人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

发明人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

IPC分类号： H01L29/66

CPC分类号： H01L27/10897 ,  H01L27/105 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.

摘要翻译： 垂直型集成电路装置包括基板和从基板垂直突出的支柱。 支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。 包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。 该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。 第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。 还讨论了相关装置和制造方法。

公开(公告)号：US20110095350A1

公开(公告)日：2011-04-28

申请号：US12891910

申请日：2010-09-28

申请人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

发明人： Jae-man Yoon ,  Hyeong-sun Hong ,  Kwang-youl Chun ,  Makoto Yoshida ,  Deok-sung Hwang ,  Chul Lee

IPC分类号： H01L27/108 ,  H01L29/78

CPC分类号： H01L27/10897 ,  H01L27/105 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/0657 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827

摘要： A vertical type integrated circuit device includes a substrate and a pillar vertically protruding from the substrate. The pillar includes a lower impurity region and an upper impurity region therein and a vertical channel region therebetween. A portion of the pillar including the lower impurity region therein includes a mesa laterally extending therefrom. The device further includes a first conductive line extending on a first sidewall of the pillar and electrically contacting the lower impurity region, and a second conductive line extending on a second sidewall of the pillar adjacent the vertical channel region. The second conductive line extends in a direction perpendicular to the first conductive line and is spaced apart from the mesa. Related devices and methods of fabrication are also discussed.

摘要翻译： 垂直型集成电路装置包括基板和从基板垂直突出的支柱。 支柱包括其中较低的杂质区域和上部杂质区域以及它们之间的垂直沟道区域。 包括其中较低杂质区域的柱的一部分包括从其横向延伸的台面。 该器件还包括在柱的第一侧壁上延伸并与下部杂质区电接触的第一导电线，以及在邻近垂直沟道区的柱的第二侧壁上延伸的第二导电线。 第二导电线在垂直于第一导电线的方向上延伸并且与台面间隔开。 还讨论了相关装置和制造方法。