公开(公告)号：US08609443B2

公开(公告)日：2013-12-17

申请号：US13666473

申请日：2012-11-01

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L21/66

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部分的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US08426909B2

公开(公告)日：2013-04-23

申请号：US13545376

申请日：2012-07-10

申请人： Naoki Yasuda

发明人： Naoki Yasuda

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/283 ,  H01L21/76224 ,  H01L23/528 ,  H01L27/10805 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/1157 ,  H01L28/40 ,  H01L28/60 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/4925 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/788 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).

公开(公告)号：US08404314B2

公开(公告)日：2013-03-26

申请号：US12294645

申请日：2007-03-23

申请人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda

发明人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda

IPC分类号： C23C8/00 ,  H01L23/58

CPC分类号： C23C16/30 ,  C23C16/342 ,  C23C16/511 ,  H01J37/32532 ,  H01L21/318

摘要： A plasma CVD apparatus including a reaction chamber including an inlet for supplying a compound including a borazine skeleton, a feeding electrode, arranged within the reaction chamber, for supporting a substrate and being applied with a negative charge, and a plasma generating mechanism, arranged opposite to the feeding electrode via the substrate, for generating a plasma within the reaction chamber. A method forms a thin film wherein a thin film is formed by using a compound including a borazine skeleton as a raw material, and a semiconductor device includes a thin film formed by such a method as an insulating film. The apparatus and method enable to produce a thin film wherein low dielectric constant and high mechanical strength are stably maintained for a long time and insulating characteristics are secured.

摘要翻译： 一种等离子体CVD装置，包括反应室，该反应室包括用于供给包含环硼氮烷骨架的化合物的入口，设置在反应室内的供电电极，用于支撑基板并施加负电荷;以及等离子体产生机构， 经由衬底到达馈电电极，用于在反应室内产生等离子体。 一种方法形成薄膜，其中通过使用包含环硼氮烷骨架的化合物作为原料形成薄膜，并且半导体器件包括通过诸如绝缘膜的方法形成的薄膜。 该装置和方法能够制造其中低介电常数和高机械强度长时间稳定地保持并且确保绝缘特性的薄膜。

公开(公告)号：US08324657B2

公开(公告)日：2012-12-04

申请号：US13160204

申请日：2011-06-14

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L29/74 ,  H01L31/111

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。

公开(公告)号：US20090232987A1

公开(公告)日：2009-09-17

申请号：US12084568

申请日：2006-11-15

申请人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Tetsuya Yamamoto ,  Yasutaka Nakatani ,  Takuya Kamiyama

发明人： Teruhiko Kumada ,  Hideharu Nobutoki ,  Naoki Yasuda ,  Tetsuya Yamamoto ,  Yasutaka Nakatani ,  Takuya Kamiyama

IPC分类号： C23C16/00 ,  C09D5/00

CPC分类号： C23C16/342 ,  C07F5/02 ,  C23C16/30 ,  H01L21/314 ,  H01L21/318

摘要： The present invention provides a composition for chemical vapor deposition film-formation comprising a borazine compound represented by the Chemical Formula 1 satisfying at least one of a condition that content of each halogen atom in the composition is 100 ppb or less or a condition that content of each metal element in the composition is 100 ppb or less. In the Chemical Formula 1, R1 may be the same or different, and is hydrogen atom, alkyl group, alkenyl group or alkynyl group, and at least one thereof is hydrogen atom; R2 may be the same or different, and is hydrogen atom, alkyl group, alkenyl group or alkynyl group, and at least one thereof is alkyl group, alkenyl group or alkynyl group. By using the composition, physical properties such as low dielectric constant property and mechanical strength of the thin film produced from a borazine-ring-containing compound can be improved.

摘要翻译： 本发明提供一种化学气相沉积膜形成用组合物，其含有化学式1表示的环硼氮烷化合物，其满足以下条件中的至少一种：组合物中的各卤素原子的含量为100ppb以下， 组合物中的每种金属元素为100ppb以下。 在化学式1中，R 1可以相同或不同，为氢原子，烷基，链烯基或炔基，其中至少一个为氢原子; R2可以相同或不同，为氢原子，烷基，烯基或炔基，其中至少一个为烷基，烯基或炔基。 通过使用该组合物，可以提高由含有环硼氮烷的化合物制造的薄膜的低介电常数性能和机械强度等物理性能。

公开(公告)号：US20080237688A1

公开(公告)日：2008-10-02

申请号：US12044645

申请日：2008-03-07

申请人： Naoki Yasuda

发明人： Naoki Yasuda

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/792

摘要： A memory cell of a nonvolatile semiconductor memory includes a first insulating film whose principal constituent elements are Si, O and N, a charge storage layer whose principal constituent elements are Hf, O and N, formed on the first insulating film, a second insulating film having dielectric constant higher than that of the first insulating film and formed on the charge storage layer, and a control gate electrode formed on the second insulating film. Relation between a composition of the first insulating film and a composition of the charge storage layer is determined under the conditions that (A) a valence band offset of the first insulating film is larger than a valence band offset of the charge storage layer, and (B) a trap energy level of electrons due to oxygen vacancies in the charge storage layer exists within a band gap of the charge storage layer.

摘要翻译： 非易失性半导体存储器的存储单元包括主要组成元素为Si，O和N的第一绝缘膜，主要组成元素为Hf，O和N的电荷存储层，形成在第一绝缘膜上，第二绝缘膜 其电介质常数高于第一绝缘膜并且形成在电荷存储层上，以及形成在第二绝缘膜上的控制栅电极。 在（A）第一绝缘膜的价带偏移大于电荷存储层的价带偏移的条件下，确定第一绝缘膜的组成与电荷存储层的组成之间的关系，以及（ B）在电荷存储层的带隙内存在由于电荷存储层中的氧空位引起的电子的陷阱能级。

公开(公告)号：US07399214B2

公开(公告)日：2008-07-15

申请号：US11416319

申请日：2006-05-03

申请人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

发明人： Kunihiko Nishimura ,  Naoki Yasuda ,  Yosuke Suzuki ,  Yoshinobu Hirokado ,  Satoru Kawamoto

IPC分类号： H01J9/24

CPC分类号： H01J9/025 ,  B82Y10/00 ,  H01J31/127 ,  H01J2201/30469

摘要： The step of forming an opening in an insulating layer to expose a carbon nanotube layer is performed using two types of dry etching different from each other in conditions. In the first-stage dry etching step, a hole is formed in the insulating layer to such a depth as not exposing the carbon nanotube layer. Thereafter, in the second-stage dry etching step, a bottom surface portion of the hole is removed, thus exposing an upper surface of the carbon nanotube layer. A method of manufacturing an electron emission source capable of improving performance of an electron emission portion is thus obtained.

摘要翻译： 在绝缘层中形成露出碳纳米管层的开口的步骤是在条件下使用彼此不同的两种类型的干蚀刻进行的。 在第一级干蚀刻步骤中，在绝缘层中形成一个不暴露碳纳米管层的深度的孔。 此后，在第二阶段干蚀刻步骤中，去除孔的底表面部分，从而暴露碳纳米管层的上表面。 由此可以得到能够提高电子发射部的性能的电子发射源的制造方法。

公开(公告)号：US20080073704A1

公开(公告)日：2008-03-27

申请号：US11822579

申请日：2007-07-09

申请人： Naoki Yasuda

发明人： Naoki Yasuda

IPC分类号： H01L29/792

CPC分类号： H01L21/28282 ,  H01L21/28088 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention provides a nonvolatile semiconductor memory device including memory cells capable of electrically writing information, and each of the memory cells includes a first insulating film formed on the channel provided between source/drain diffusion layers, an electric charge accumulation layer formed on the first insulating film and is made of nitride or oxynitride containing at least one selected from Si, Ge, Ga, and Al, a donor layer containing n-type dopant impurity formed on the electric charge accumulation layer and is made of nitride or oxynitride containing at least one selected from among Si, Ge, Ga, and Al, a second insulating film formed on the donor layer, and a control gate electrode formed on the second insulating film.

摘要翻译： 本发明提供了一种包括能够电气写入信息的存储单元的非易失性半导体存储器件，并且每个存储单元包括形成在源/漏扩散层之间的沟道上的第一绝缘膜，形成在第一 绝缘膜，并且由含有选自Si，Ge，Ga和Al中的至少一种的氮化物或氮氧化物制成，包含形成在电荷蓄积层上的n型掺杂杂质的施主层，并且由至少包含氮化物或氧氮化物 选自Si，Ge，Ga和Al中的一种，在施主层上形成的第二绝缘膜，以及形成在第二绝缘膜上的控制栅电极。

公开(公告)号：US20080038585A1

公开(公告)日：2008-02-14

申请号：US11575874

申请日：2005-10-07

申请人： Teruhiko Kumada ,  Naoki Yasuda ,  Hideharu Nobutoki ,  Norihisa Matsumoto ,  Shigeru Matsuno

发明人： Teruhiko Kumada ,  Naoki Yasuda ,  Hideharu Nobutoki ,  Norihisa Matsumoto ,  Shigeru Matsuno

IPC分类号： C23C8/00

CPC分类号： C23C16/38 ,  H01L21/318 ,  H01L21/76801

摘要： The present invention provides a method of manufacturing a film including the steps of using a compound with borazine skeleton (preferably a compound expressed by a chemical formula (1) below (where R1-R6 may be identical with or different from each other, and are each independently selected from a group consisting of a hydrogen atom, and an alkyl group, an alkenyl group and an alkynyl group each having a carbon number of 1-4, on condition that at least one of R1-R6 is not the hydrogen atom)) as a raw material, and forming the film on a substrate by using a chemical vapor deposition method, characterized in that a negative charge is applied to a site for placing the substrate, and a semiconductor device utilizing a film manufactured by the method. With the present invention, it is possible to provide a method of manufacturing a film, which method stably provides a low dielectric constant and a high mechanical strength over a long period of time, reduces the amount of a gas component (outgas) emitted in heating the film, and avoids any trouble in the device manufacturing process.

摘要翻译： 本发明提供一种膜的制造方法，其包括使用具有环硼氮烷骨架的化合物（优选以下述化学式（1）表示的化合物（其中R 1〜R 6） 并且各自独立地选自氢原子和烷基，链烯基和各自具有碳数为1-4的炔基， 条件是R 1 -R 6中的至少一个不是氢原子））作为原料，并且通过使用化学气相在基板上形成该膜 沉积方法，其特征在于将负电荷施加到用于放置所述衬底的位置，以及利用通过所述方法制造的膜的半导体器件。 通过本发明，可以提供一种膜的制造方法，该方法在长时间内稳定地提供低介电常数和高机械强度，减少了在加热中排出的气体成分（废气）的量 并避免了设备制造过程中的任何麻烦。

公开(公告)号：US20070072394A1

公开(公告)日：2007-03-29

申请号：US11412990

申请日：2006-04-28

申请人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

发明人： Kazuhiro Shimizu ,  Hajime Akiyama ,  Naoki Yasuda

IPC分类号： H01L21/00

CPC分类号： H01L21/67271 ,  H01L21/67282 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device manufacturing apparatus is provided with a drawing pattern printing part having a print head which injects a conductive solvent, an insulative solvent and an interface treatment solution. The print head is formed in such a way that desired circuit drawing pattern can be printed on a wafer based on information on the drawing pattern from a wafer testing part, information on the wafer from a storage part and coordinate information from a chip coordinate recognition part. In a semiconductor device manufacturing method according to the present invention, a semiconductor device is manufactured by using the semiconductor device manufacturing apparatus in such a manner that desired circuits are formed through printing process. In the semiconductor device, pad electrodes and so on are formed in such a way that trimming process can be conducted by printing circuit drawing patterns.

摘要翻译： 半导体器件制造装置具备：具有喷射导电性溶剂的印刷头，绝缘性溶剂和界面处理液的图形印刷部。 打印头形成为使得可以基于来自晶片测试部件的绘图图案的信息，从存储部分获得关于晶片的信息和来自芯片坐标识别部分的坐标信息，将期望的电路图形图案印刷在晶片上 。 在根据本发明的半导体器件制造方法中，通过使用半导体器件制造设备以通过印刷处理形成期望的电路的方式制造半导体器件。 在半导体器件中，焊盘电极等以能够通过打印电路图形进行修整处理的方式形成。