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137 条记录 (耗时 0.048 秒)

    Semiconductor memory device and method of programming the same
    82.
    发明授权
    Semiconductor memory device and method of programming the same 有权
    半导体存储器件及其编程方法

    公开(公告)号：US07672154B2

    公开(公告)日：2010-03-02

    申请号：US12073678

    申请日：2008-03-07

    申请人： In-jun Hwang ,  Hyung-soon Shin ,  Seung-jun Lee ,  Sun-ae Seo ,  Kee-won Kim ,  Kwang-seok Kim

    发明人： In-jun Hwang ,  Hyung-soon Shin ,  Seung-jun Lee ,  Sun-ae Seo ,  Kee-won Kim ,  Kwang-seok Kim

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1697 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675

    摘要： Provided are a semiconductor memory device and a method of programming the same. The semiconductor memory device includes a mode input value generating unit and a logic operating unit. The mode input value generating unit changes a connection state between input values of a current driving circuit so as to correspond to each of at least two operating modes, and defines a logic function of a magnetic memory cell connected to the current driving circuit in response to each operating mode. The logic operating unit performs a logic operation on the logic functions of at least two magnetic memory cells defined according to each of the operating modes and generates a result of logic operation.

    摘要翻译： 提供一种半导体存储器件及其编程方法。 半导体存储器件包括模式输入值生成单元和逻辑运算单元。 模式输入值生成单元将当前驱动电路的输入值之间的连接状态改变为对应于至少两种操作模式中的每一种，并且响应于所述至少两种操作模式而连接到当前驱动电路的磁存储单元的逻辑功能 每个操作模式。 逻辑操作单元对根据每个操作模式定义的至少两个磁存储器单元的逻辑功能进行逻辑运算，并产生逻辑运算的结果。

    Information storage devices using magnetic domain wall movement and methods of manufacturing the same
    83.
    发明申请
    Information storage devices using magnetic domain wall movement and methods of manufacturing the same 失效
    使用磁畴壁运动的信息存储装置及其制造方法相同

    公开(公告)号：US20090130492A1

    公开(公告)日：2009-05-21

    申请号：US12149641

    申请日：2008-05-06

    申请人： Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Chang-won Lee

    发明人： Sung-chul Lee ,  Sun-ae Seo ,  Young-jin Cho ,  Chang-won Lee

    IPC分类号： G11B5/62 ,  G11B5/73 ,  B05D3/10 ,  B05D1/36 ,  B05D3/00

    CPC分类号： G11B5/855 ,  G11B5/7325 ,  G11C11/14 ,  G11C19/0841

    摘要： Information storage devices and methods of manufacturing the same are provided. An information storage device includes a magnetic layer formed on an underlayer. The underlayer has at least one first region and at least one second region. The first and second regions have different crystallinity characteristics. The magnetic layer has at least one third region formed on the at least one first region and at least one fourth region formed on the at least one second region. The third and fourth regions have different magnetic anisotropic energy constants.

    摘要翻译： 提供信息存储装置及其制造方法。 信息存储装置包括形成在底层上的磁性层。 底层具有至少一个第一区域和至少一个第二区域。 第一和第二区域具有不同的结晶度特性。 磁性层具有形成在至少一个第一区域上的至少一个第三区域和形成在至少一个第二区域上的至少一个第四区域。 第三和第四区域具有不同的磁各向异性能量常数。

    Memory device and method of manufacturing the same
    85.
    发明授权
    Memory device and method of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号：US07491997B2

    公开(公告)日：2009-02-17

    申请号：US11002812

    申请日：2004-12-03

    申请人： In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

    发明人： In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

    IPC分类号： H01L29/76

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833

    摘要： A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.

    摘要翻译： 提供了一种存储器件及其制造方法。 该方法包括在半导体衬底上形成栅极叠层，并通过蚀刻栅叠层来部分地暴露半导体衬底的上端部分以形成栅叠层结构，并将掺杂剂注入半导体衬底的暴露部分以形成源极和漏极 区域，其中蚀刻栅极堆叠结构，使得其宽度从顶部向底部增加。 因此，可以使用简化的制造工艺来制造具有高集成度的存储器件。

    METHOD OF MANUFACTURING SELF-ORDERED NANOCHANNEL-ARRAY AND METHOD OF MANUFACTURING NANODOT USING THE NANOCHANNEL-ARRAY
    87.
    发明申请
    METHOD OF MANUFACTURING SELF-ORDERED NANOCHANNEL-ARRAY AND METHOD OF MANUFACTURING NANODOT USING THE NANOCHANNEL-ARRAY 有权
    自制纳米管阵列的制造方法及使用纳米通道阵列制造纳米光的方法

    公开(公告)号：US20070207619A1

    公开(公告)日：2007-09-06

    申请号：US10819143

    申请日：2004-04-07

    申请人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

    发明人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： B82B3/00 ,  B29C59/022 ,  B29C59/026 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/32139

    摘要： A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

    摘要翻译： 提供一种制造纳米通道阵列的方法和使用纳米通道阵列制造纳米点的方法。 纳米通道阵列制造方法包括：执行第一阳极氧化以形成具有由铝基板上的多个空腔形成的沟道阵列的第一氧化铝层; 将第一氧化铝层蚀刻到预定深度并在铝基板上形成多个凹部，其中每个凹部对应于第一氧化铝层的每个通道的底部; 以及进行第二阳极氧化以形成具有与所述铝基板上的所述多个凹部对应的多个通道的阵列的第二氧化铝层。 阵列制造方法使得可以使用空腔获得精细排列的空腔并形成纳米级点。

    Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device
    88.
    发明申请
    Multi-bit non-volatile memory device, method of operating the same, and method of manufacturing the multi-bit non-volatile memory device 失效
    多位非易失性存储器件，其操作方法以及制造多位非易失性存储器件的方法

    公开(公告)号：US20060097308A1

    公开(公告)日：2006-05-11

    申请号：US11181724

    申请日：2005-07-15

    申请人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

    发明人： Yoon-dong Park ,  Sun-ae Seo ,  Choong-rae Cho ,  Won-joo Kim ,  Sang-min Shin

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L29/7926 ,  H01L29/42332 ,  H01L29/7887 ,  H01L29/7923

    摘要： Disclosed are a muli-bit non-volatile memory device, a method of operating the same, and a method of manufacturing the multi-bit non-volatile memory device. A unit cell of the muli-bit non-volatile memory device may be formed on a semiconductor substrate may include: a plurality of channels disposed perpendicularly to the upper surface of the semiconductor substrate; a plurality of storage nodes disposed on opposite sides of the channels perpendicularly the upper surface of the semiconductor substrate; a control gate surrounding upper portions of the channels and the storage nodes, and side surfaces of the storage nodes; and an insulating film formed between the channels and the storage nodes, between the channels and the control gate, and between the storage nodes and the control gate.

    摘要翻译： 公开了多位非易失性存储器件，其操作方法以及制造多位非易失性存储器件的方法。 多晶硅非易失性存储器件的单元可以形成在半导体衬底上，可以包括：垂直于半导体衬底的上表面设置的多个沟道; 多个存储节点，其设置在所述通道的相对侧，垂直于所述半导体衬底的上表面; 围绕通道和存储节点的上部以及存储节点的侧表面的控制门; 以及形成在通道和存储节点之间，通道和控制栅极之间以及存储节点和控制门之间的绝缘膜。