公开(公告)号：US20220359447A1

公开(公告)日：2022-11-10

申请号：US17869118

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/54

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

公开(公告)号：US20220359406A1

公开(公告)日：2022-11-10

申请号：US17869286

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chun-Chih Chuang ,  Kuan-Lin Ho ,  Yu-Min Liang ,  Jiun Yi Wu

IPC: H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31

Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.

公开(公告)号：US11462507B2

公开(公告)日：2022-10-04

申请号：US17034917

申请日：2020-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Chia-Shen Cheng ,  Hao-Jan Pei ,  Philip Yu-Shuan Chung ,  Kuei-Wei Huang ,  Yu-Peng Tsai ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56

Abstract: A method includes performing a first laser shot on a first portion of a top surface of a first package component. The first package component is over a second package component, and a first solder region between the first package component and the second package component is reflowed by the first laser shot. After the first laser shot, a second laser shot is performed on a second portion of the top surface of the first package component. A second solder region between the first package component and the second package component is reflowed by the second laser shot.

公开(公告)号：US11410956B2

公开(公告)日：2022-08-09

申请号：US17106941

申请日：2020-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Li-Hsien Huang ,  An-Jhih Su ,  Hsien-Wei Chen

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/065 ,  H01L23/498 ,  H01L21/56 ,  H01L25/00 ,  H01L21/48 ,  H01L21/54

Abstract: A chip package structure is provided. The chip package structure includes a redistribution structure and a first chip structure over the redistribution structure. The chip package structure also includes a first solder bump between the redistribution structure and the first chip structure and a first molding layer surrounding the first chip structure. The chip package structure further includes a second chip structure over the first chip structure and a second molding layer surrounding the second chip structure. In addition, the chip package structure includes a third molding layer surrounding the first molding layer, the second molding layer, and the first solder bump. A portion of the third molding layer is between the first molding layer and the redistribution structure.

公开(公告)号：US20220216071A1

公开(公告)日：2022-07-07

申请号：US17141835

申请日：2021-01-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  Hao-Jan Pei ,  Hsuan-Ting Kuo ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Philip Yu-Shuan Chung ,  Chia-Lun Chang ,  Hsiu-Jen Lin ,  Ching-Hua Hsieh

IPC: H01L21/50 ,  H01L23/00 ,  H01L21/48

Abstract: A method includes forming regions of solder paste on a redistribution structure, wherein the solder paste has a first melting temperature; forming solder bumps on an interconnect structure, wherein the solder bumps have a second melting temperature that is greater than the first melting temperature; placing the solder bumps on the regions of solder paste; performing a first reflow process at a first reflow temperature for a first duration of time, wherein the first reflow temperature is less than the second melting temperature; and after performing the first reflow process, performing a second reflow process at a second reflow temperature for a second duration of time, wherein the second reflow temperature is greater than the second melting temperature.

公开(公告)号：US20220020655A1

公开(公告)日：2022-01-20

申请号：US16933910

申请日：2020-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jung-Wei Cheng ,  Jiun-Yi Wu ,  Hsin-Yu Pan ,  Tsung-Ding Wang ,  Yu-Min Liang ,  Wei-Yu Chen

IPC: H01L23/31 ,  H01L23/538 ,  H01L23/40

Abstract: A semiconductor package includes a circuit board structure, a first redistribution layer structure and first bonding elements. The circuit board structure includes outermost first conductive patterns and a first mask layer adjacent to the outermost first conductive patterns. The first redistribution layer structure is disposed over the circuit board structure. The first bonding elements are disposed between and electrically connected to the first redistribution layer structure and the outermost first conductive patterns of the circuit board structure. In some embodiments, at least one of the first bonding elements covers a top and a sidewall of the corresponding outermost first conductive pattern.

公开(公告)号：US11217553B2

公开(公告)日：2022-01-04

申请号：US16587539

申请日：2019-09-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Jen Tseng ,  Wei-Yu Chen ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/528 ,  H01L25/00 ,  H01L21/768 ,  H01L23/48 ,  H01L21/822 ,  H01L27/06 ,  H01L23/535 ,  H01L21/74 ,  H01L25/07 ,  H01L27/118 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.

公开(公告)号：US11211341B2

公开(公告)日：2021-12-28

申请号：US16719984

申请日：2019-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hao-Jan Pei ,  Ching-Hua Hsieh ,  Hsiu-Jen Lin ,  Wei-Yu Chen ,  Chia-Shen Cheng ,  Chih-Chiang Tsao ,  Jen-Jui Yu ,  Cheng-Shiuan Wong

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: Provided is a package structure, including a die, a plurality of through vias, an encapsulant, a plurality of first connectors, a warpage control material and a protection material. The plurality of through vias are disposed around the die. The encapsulant laterally encapsulate the die and the plurality of through vias. The plurality of first connectors are electrically connected to the plurality of through vias. The warpage control material is disposed over a first surface of the die. The protection material is disposed over the encapsulant, around the plurality of first connectors and the warpage control material.

公开(公告)号：US11145633B2

公开(公告)日：2021-10-12

申请号：US16795523

申请日：2020-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Yu Chen ,  An-Jhih Su ,  Li-Hsien Huang ,  Tien-Chung Yang ,  Ming-Shih Yeh

IPC: H01L25/10 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a semiconductor die an insulating encapsulation laterally covering the semiconductor die. The semiconductor die includes a semiconductor substrate, a plurality of conductive pads distributed over the semiconductor substrate, a plurality of conductive vias disposed on and electrically connected to the conductive pads, and a dielectric layer disposed over the semiconductor substrate and spaced the conductive vias apart from one another. A sidewall of the dielectric layer extends along sidewalls of the conductive vias, the conductive vias are recessed from a top surface of the dielectric layer, and a sloped surface of the dielectric layer is connected to the top surface of the dielectric layer and the sidewall of the dielectric layer.

公开(公告)号：US10658323B2

公开(公告)日：2020-05-19

申请号：US16398119

申请日：2019-04-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Hao-Jan Pei ,  Chih-Chiang Tsao ,  Wei-Yu Chen ,  Hsiu-Jen Lin ,  Ming-Da Cheng ,  Ching-Hua Hsieh ,  Chung-Shi Liu

IPC: H01L21/00 ,  H01L23/00 ,  H01L25/11 ,  H01L25/10 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31 ,  H01L21/683

Abstract: A package structure is provided. The package structure includes a semiconductor die and a protective layer surrounding the semiconductor die. The package structure also includes a conductive structure and a warpage-control element over a same side of the protective layer. A bottom surface of the warpage-control element is higher than a bottom surface of the conductive structure. The bottom surface of the warpage-control element is lower than a top surface of the conductive bump.