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    WAFER HOLDER FOR FILM DEPOSITION CHAMBER
    81.
    发明申请
    WAFER HOLDER FOR FILM DEPOSITION CHAMBER 有权

    公开(公告)号：US20210118700A1

    公开(公告)日：2021-04-22

    申请号：US16657841

    申请日：2019-10-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsuan-Chih Chu ,  Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

    IPC: H01L21/673 ,  H01L21/67 ,  H01L21/687 ,  H01L21/66

    Abstract: The present disclosure provides a flexible workpiece pedestal capable of tilting a workpiece support surface. The workpiece pedestal further includes a heater mounted on the workpiece support surface. The heater includes a plurality of heating sources such as heating coils. The plurality of heating sources in the heater allows heating the workpiece at different temperatures for different zones of the workpiece. For example, the workpiece can have a central zone heated by a first heating coil, a first outer ring zone that is outside of the central zone heated by a second heating coil, a second outer ring zone that is outside of the first outer ring zone heated by a third heating coil. By using the tunable heating feature and the tilting feature of the workpiece pedestal, the present disclosure can reduce or eliminate the shadowing effect problem of the related workpiece pedestal in the art.

    Mechanisms for monitoring impurity in high-K dielectric film
    86.
    发明授权
    Mechanisms for monitoring impurity in high-K dielectric film 有权
    监测高K电介质膜杂质的机理

    公开(公告)号：US09553160B2

    公开(公告)日：2017-01-24

    申请号：US14049657

    申请日：2013-10-09

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Jen Chen ,  Yen-Yu Chen ,  Chang-Sheng Lee ,  Wei Zhang

    IPC: H01L21/66 ,  G01R31/26 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

    CPC classification number: H01L29/4966 ,  H01L21/28194 ,  H01L22/12 ,  H01L22/20 ,  H01L29/513 ,  H01L29/517

    Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.

    Abstract translation: 提供了在高k电介质膜中监测金属杂质的机理的实施例。 该方法包括在衬底上形成界面层。 该方法还包括在界面层上形成高k电介质膜，并且界面层和高k电介质膜在衬底上形成堆叠结构。 该方法还包括对堆叠结构进行第一厚度测量。 此外，该方法包括在第一厚度测量之后对堆叠结构进行处理，并且处理包括退火处理。 该方法还包括在处理之后对堆叠结构进行第二厚度测量。

    Semiconductor device with tunable work function
    87.
    发明授权
    Semiconductor device with tunable work function 有权
    具有可调功能的半导体器件

    公开(公告)号：US09548372B2

    公开(公告)日：2017-01-17

    申请号：US14609138

    申请日：2015-01-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Wei Zhang

    IPC: H01L29/51 ,  H01L29/423

    CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/511 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/78

    Abstract: The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

    Abstract translation: 金属氧化物半导体结构包括衬底，栅极电介质多层，蚀刻停止层，功函数金属层，阻挡层和硅化物层。 衬底具有沟槽。 栅极电介质多层覆盖沟槽，其中栅极电介质多层包括氟浓度基本上在1at％至10at％范围内的高k覆盖层。 蚀刻停止层设置在栅极电介质多层上。 功函数金属层设置在蚀刻停止层上。 阻挡层设置在功函数金属层上。 硅化物层设置在阻挡层上。

    Barrier layer for metal insulator metal capacitors
    88.
    发明授权
    Barrier layer for metal insulator metal capacitors 有权

    公开(公告)号：US12211890B2

    公开(公告)日：2025-01-28

    申请号：US17815524

    申请日：2022-07-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Anhao Cheng ,  Fang-Ting Kuo ,  Yen-Yu Chen

    IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02

    Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.

    Gate structures for tuning threshold voltage
    89.
    发明授权
    Gate structures for tuning threshold voltage 有权

    公开(公告)号：US12205850B2

    公开(公告)日：2025-01-21

    申请号：US17810799

    申请日：2022-07-05

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

    IPC: H01L21/8238 ,  H01L21/033 ,  H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/78

    Abstract: A semiconductor device includes a first gate structure that includes a first interfacial layer, a first gate dielectric layer disposed over the first interfacial layer, and a first gate electrode disposed over the first gate dielectric layer. The semiconductor device also includes a second gate structure that includes a second interfacial layer, a second gate dielectric layer disposed over the second interfacial layer, and a second gate electrode disposed over the second gate dielectric layer. The first interfacial layer contains a different amount of a dipole material than the second interfacial layer.

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