公开(公告)号：US07496261B2

公开(公告)日：2009-02-24

申请号：US11203890

申请日：2005-08-15

申请人： Kazuhiko Aikawa ,  Yutaka Nagasawa ,  Shogo Shimizu ,  Takaaki Suzuki ,  Masakazu Nakayama ,  Kuniharu Himeno ,  Ryozo Yamauchi ,  Keiji Ohashi ,  Munehisa Fujimaki

发明人： Kazuhiko Aikawa ,  Yutaka Nagasawa ,  Shogo Shimizu ,  Takaaki Suzuki ,  Masakazu Nakayama ,  Kuniharu Himeno ,  Ryozo Yamauchi ,  Keiji Ohashi ,  Munehisa Fujimaki

IPC分类号： G02B6/036

CPC分类号： G02B6/02009 ,  G02B6/02261 ,  G02B6/0228 ,  G02B6/02395 ,  G02B6/03627 ,  G02B6/03644

摘要： A dispersion compensating optical fiber for NZ-DSFs, includes: an uncovered dispersion compensating optical fiber; a double-layered resin coating disposed around the uncovered dispersion compensating optical fiber; and an outer coating layer having a thickness of 3 to 7 μm, containing silicone in an amount of 1 to 5% by weight, and disposed around the double-layered resin coating. The outer diameter of the uncovered dispersion compensating optical fiber is in a range from 90 to 125 μm, an outer diameter of the dispersion compensating optical fiber is in a range from 180 to 250 μm, and the amount of silicone contained in the outer coating layer is determined such that an adhesive property of the outer coating layer is 1 gf/mm or less.

摘要翻译： 用于NZ-DSF的色散补偿光纤包括：未覆盖的色散补偿光纤; 设置在未覆盖的色散补偿光纤周围的双层树脂涂层; 以及厚度为3〜7μm的外涂层，含有1〜5重量％的硅氧烷，并且设置在双层树脂涂层的周围。 未覆盖的色散补偿光纤的外径在90〜125μm的范围内，色散补偿光纤的外径在180〜250μm的范围内，外涂层的硅氧烷的含量 确定为外涂层的粘合性为1gf / mm以下。

公开(公告)号：US20080284935A1

公开(公告)日：2008-11-20

申请号：US12119547

申请日：2008-05-13

申请人： Takuya Takahashi ,  Takaaki Suzuki

发明人： Takuya Takahashi ,  Takaaki Suzuki

IPC分类号： H01L21/782 ,  G02F1/1368

CPC分类号： G02F1/136286 ,  G02F2001/13629 ,  H01L27/124 ,  H01L29/458

摘要： Disclosed is a liquid crystal display device having a signal line of low electrical resistivity and high adhesion with an underlayer, wherein a copper alloy film is formed on an underlayer, and an oxide film, silicide film or nitride film, which are additive metal elements of the copper alloy, is formed at the boundary between the underlayer and the copper alloy film whereby the signal line is formed with a multi-layer film of the copper alloy film and the oxide film, the silicide film, or the nitride film.

摘要翻译： 公开了一种液晶显示装置，其具有低电阻率信号线和与底层粘合性高的信号线，其中在底层上形成铜合金膜，以及氧化物膜，硅化物膜或氮化物膜，它们是添加金属元素 铜合金形成在底层和铜合金膜之间的边界处，由此由铜合金膜和氧化物膜，硅化物膜或氮化物膜的多层膜形成信号线。

公开(公告)号：US07366433B2

公开(公告)日：2008-04-29

申请号：US11182406

申请日：2005-07-15

申请人： Takaaki Suzuki ,  Takaharu Ouchi

发明人： Takaaki Suzuki ,  Takaharu Ouchi

IPC分类号： G03G15/00

CPC分类号： G03G15/507

摘要： An image forming apparatus may include an image acquiring section for acquiring the image to be printed, an attribute information acquiring section for acquiring attribute information of the recording sheet to be used for printing the image acquired by the image acquiring section from the IC tag attached to the recording sheet and storing the attribute information, a printing control section for controlling the operation of printing the image so as to make the image match the attributes of the recording sheet on the basis of the attribute information acquired by the attribute information acquiring section and an image printing section for printing the image under the control of the printing control section.

摘要翻译： 图像形成装置可以包括用于获取要打印的图像的图像获取部分，属性信息获取部分，用于从附加到所述图像获取部分的IC标签获取用于打印由图像获取部分获取的图像的记录纸张的属性信息 记录纸张并存储属性信息;打印控制部分，用于控制打印图像的操作，以使图像根据由属性信息获取部分获取的属性信息与记录纸张的属性相匹配;以及 图像打印部分，用于在打印控制部分的控制下打印图像。

公开(公告)号：US20060294322A1

公开(公告)日：2006-12-28

申请号：US11512319

申请日：2006-08-30

申请人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

发明人： Yasurou Matsuzaki ,  Takaaki Suzuki ,  Masafumi Yamazaki ,  Kenichi Kawasaki ,  Shinnosuke Kamata ,  Ayako Sato ,  Masato Matsumiya

IPC分类号： G06F13/28

CPC分类号： G11C8/16 ,  G06F13/1605 ,  G11C7/1039 ,  G11C7/1075 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/18 ,  G11C11/24 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/409 ,  G11C11/4093 ,  G11C2207/107 ,  G11C2207/108

摘要： A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.

公开(公告)号：US07138723B2

公开(公告)日：2006-11-21

申请号：US11006664

申请日：2004-12-08

申请人： Kazuyuki Aiba ,  Akira Takashima ,  Kaname Ozawa ,  Tetsuya Hiraoka ,  Takaaki Suzuki ,  Yasurou Matsuzaki

发明人： Kazuyuki Aiba ,  Akira Takashima ,  Kaname Ozawa ,  Tetsuya Hiraoka ,  Takaaki Suzuki ,  Yasurou Matsuzaki

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L29/06 ,  H01L23/28 ,  H01L29/02

CPC分类号： H01L29/0657 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/81 ,  H01L25/065 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/3511

摘要： A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.

摘要翻译： 通过在其表面上形成的涂层材料将半导体芯片固定成大致圆柱形状的状态。 变形的半导体芯片倒装芯片连接到插入器并用密封树脂密封到插入器上。 焊球作为外部端子设置在插入器的另一侧。

公开(公告)号：US07071053B2

公开(公告)日：2006-07-04

申请号：US10852121

申请日：2004-05-25

申请人： Toshihide Nabatame ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Kazutoshi Higashiyama

发明人： Toshihide Nabatame ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Kazutoshi Higashiyama

IPC分类号： H01L21/8242

CPC分类号： H01L28/55 ,  C23C16/18 ,  C23C16/40 ,  H01L28/60

摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

摘要翻译： 提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。 通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，该底部电极46和顶部电极48包括具有100％阶梯覆盖的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上， 通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。

公开(公告)号：US06821845B1

公开(公告)日：2004-11-23

申请号：US09806861

申请日：2001-04-05

申请人： Toshihide Nabatame ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Kazutoshi Higashiyama

发明人： Toshihide Nabatame ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Kazutoshi Higashiyama

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  C23C16/18 ,  C23C16/40 ,  H01L28/60

摘要： A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

摘要翻译： 提供一种半导体器件，其包含对于高集成度的高纵横比的器件结构具有优异的阶梯覆盖的介电电容器及其制造方法。 通过形成底部电极46和顶部电极48来制造高集成度的介电电容器，底部电极46和顶部电极48包括具有100％台阶覆盖率的均匀的薄Ru膜，同时将电介质47放置在具有三维结构的基板44,45上， 通过使用环戊二烯基络合物的MOCVD法在180℃以上至250℃以下的温度范围内的纵横比为3以上。

公开(公告)号：US06496934B2

公开(公告)日：2002-12-17

申请号：US09727453

申请日：2000-12-04

申请人： Takaaki Suzuki ,  Tomoya Takasuga ,  Norio Nakagawa

发明人： Takaaki Suzuki ,  Tomoya Takasuga ,  Norio Nakagawa

IPC分类号： G06F1214

CPC分类号： G06F12/1433

摘要： A combination mode a data transfer for a transfer source and a transfer destination is previously defined by a value of resource select information of a control register (CHCRn). An address comparator circuit (SACn, DACn) has judging logic specified by the defined contents and detects, depending on its logical structure, a data transfer address error in the a data transfer controller (8) on the basis of such logical structure, in accordance with resource select information and the transfer source address and transfer destination address of the address registers (SARn, DARn). Since the data transfer is started only when the resource select information matches with the setting information of both address registers, high reliability can be assured for memory protection in the data transfer operation by the data transfer controller.

摘要翻译： 预先通过控制寄存器（CHCRn）的资源选择信息的值来定义用于传送源和传送目的地的数据传输的组合模式。 地址比较器电路（SACn，DACn）具有由定义的内容指定的判断逻辑，根据其逻辑结构，根据这种逻辑结构检测数据传输控制器（8）中的数据传输地址错误 具有资源选择信息和地址寄存器（SARn，DARn）的传输源地址和传送目标地址。 由于仅当资源选择信息与两个地址寄存器的设置信息匹配时才开始数据传输，所以可以确保数据传送控制器在数据传送操作中的存储器保护的高可靠性。

公开(公告)号：US06493774B2

公开(公告)日：2002-12-10

申请号：US09776892

申请日：2001-02-06

申请人： Takaaki Suzuki ,  Tomoya Takasuga ,  Atsushi Hasegawa

发明人： Takaaki Suzuki ,  Tomoya Takasuga ,  Atsushi Hasegawa

IPC分类号： G06F1300

CPC分类号： G06F13/28

摘要： An input/output device used as a transfer request source outputs a data transfer set command for specifying each transfer channel, each transfer address, the number of transfers, etc. onto a bus together with a data transfer request without being involving use of the CPU. According to the data transfer set command, data transfer control information is set to direct memory access control means, and DMA transfer is started between the input/output device and a memory designated by the transfer address, for example. When the input/output device used as a data transfer request source desires to perform data transfer without regard to a state of processing by the microcomputer, it can perform data transfer processing with its own timing and the data transfer with the input/output device as a principal base is allowed.

摘要翻译： 用作传送请求源的输入/输出设备输出用于指定每个传送通道，每个传送地址，传送次数等的数据传送设置命令与数据传送请求一起而不涉及CPU的使用 。 根据数据传送设定命令，数据传送控制信息被设置为直接存储器访问控制装置，并且例如在输入/输出装置和由传送地址指定的存储器之间开始DMA传送。 当用作数据传送请求源的输入/输出设备希望执行数据传输而不考虑微处理器的处理状态时，它可以利用其自身的定时和与输入/输出设备的数据传输进行数据传输处理，作为 主要基地是允许的。

公开(公告)号：US06483167B1

公开(公告)日：2002-11-19

申请号：US09644716

申请日：2000-08-23

申请人： Toshihide Nabatame ,  Masaru Kadoshima ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Seiji Watahiki ,  Yasuhiko Murata ,  Mitsuo Hayashibara

发明人： Toshihide Nabatame ,  Masaru Kadoshima ,  Takaaki Suzuki ,  Tetsuo Fujiwara ,  Seiji Watahiki ,  Yasuhiko Murata ,  Mitsuo Hayashibara

IPC分类号： H01L2900

CPC分类号： H01L28/60 ,  H01L28/55 ,  H01L28/91

摘要： In a semiconductor device and production method thereof, a technique is used to prevent film separation of the bottom electrode occurring during a heat treatment process which is carried out to make the bottom electrode closely packed and in the heat treatment process for producing dielectric crystallization. In the production method, a glue layer including an insulator is formed between SiO2 insulation layer and the inner wall of a concave hole. The SiO2 layer 14 is located on the Si board 11, and Si plug 12 and a barrier layer 13 are formed therein. A glue layer 16 is formed on the inner wall of the hole of the SiO2 insulation layer 15, and a bottom electrode 17 comprising Ru is formed on the barrier layer 13 and glue layer 16. Dielectric film 18 comprising BST and a top electrode 19 comprising Ru are laminated sequentially on the bottom electrode 17, to form a dielectric device with the bottom electrode 17.

摘要翻译： 在半导体装置及其制造方法中，使用这样的技术来防止在进行底部电极紧密堆积的热处理过程中发生的底部电极的膜分离和用于产生电介质结晶的热处理工艺。 在制造方法中，在SiO2绝缘层和凹孔的内壁之间形成包含绝缘体的胶层。 SiO 2层14位于Si基板11上，形成Si塞12和阻挡层13。 在SiO 2绝缘层15的孔的内壁上形成胶层16，在阻挡层13和胶层16上形成包含Ru的底部电极17.包含BST的电介质膜18和顶部电极19包括 Ru依次层叠在底部电极17上，形成具有底部电极17的电介质器件。