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218 条记录 (耗时 0.041 秒)

    FLUOROPHORES
    82.
    发明申请
    FLUOROPHORES 失效
    氟化物

    公开(公告)号：US20110025194A1

    公开(公告)日：2011-02-03

    申请号：US12933382

    申请日：2009-03-18

    申请人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

    发明人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

    IPC分类号： C09K11/66 ,  H01J1/62 ,  C09K11/54 ,  C09K11/59

    CPC分类号： C09K11/7734 ,  H01J61/44

    摘要： Provided are phosphors that can exhibit higher emission luminance. Phosphors in which the activator is included in a compound represented by Formula xM1O.M2O.yM3O2 (wherein M1 represents one or more of a group comprising Ca, Sr and Ba, M2 represents Mg and/or Zn, M3 represents Si and/or Ge, x is a value in the range 4 to 6 and y is a value in the range 2 to 4). Phosphors represented by Formula M15(1−z)EuzM2M33O12 (wherein M1, M2 and M3 have the same meanings as above, and z is a value in the range 0.0001 to 0.3). The above phosphors have the same crystal structure as bredigite.

    摘要翻译： 提供可以表现出更高发光亮度的荧光体。 其中活化剂包括在由式xM1O.M2O.yM3O2表示的化合物中的荧光体（其中M1表示包含Ca，Sr和Ba的一种或多种，​​M2表示Mg和/或Zn，M3表示Si和/或Ge ，x是4〜6的范围内的值，y是2〜4的范围的值）。 由式M15（1-z）表示的荧光体EuzM2M33O12（其中M1，M2和M3具有与上述相同的含义，z是0.0001至0.3的范围内的值）。 上述荧光体具有与白云石相同的晶体结构。

    Method for Forming Self-Assembled Monolayer Film, and Structural Body and Field-Effect Transistor Having Same
    83.
    发明申请
    Method for Forming Self-Assembled Monolayer Film, and Structural Body and Field-Effect Transistor Having Same 审中-公开
    形成自组装单层膜的方法，以及具有相同结构体和场效应晶体管的方法

    公开(公告)号：US20090297868A1

    公开(公告)日：2009-12-03

    申请号：US12127605

    申请日：2008-05-27

    申请人： Yutaka Ito ,  Zhenan Bao ,  Jason Locklin

    发明人： Yutaka Ito ,  Zhenan Bao ,  Jason Locklin

    IPC分类号： B05D3/12 ,  B05D3/02 ,  B32B9/04

    CPC分类号： H01L51/0533 ,  H01L51/0545 ,  Y10T428/31663

    摘要： A method for forming a self-organized monomolecular film, including at least: dissolving an alkylsilane compound having at least an alkoxysilane group or a chlorosilane group at one end of a molecule in an organic solvent having a dielectric constant of 3.0 or more to 6.0 or less to obtain a solution; subsequently coating the solution on a base material or immersing the base material into the solution; and subsequently drying the solution located on the base material.

    摘要翻译： 一种形成自组织单分子膜的方法，至少包括：将分子一端具有至少烷氧基硅烷基或氯硅烷基的烷基硅烷化合物溶解在介电常数为3.0以上至6.0的有机溶剂中，或 较少获得解决方案; 随后将溶液涂覆在基材上或将基材浸入溶液中; 随后干燥位于基材上的溶液。

    Semiconductor memory device and refresh period controlling method
    84.
    发明申请
    Semiconductor memory device and refresh period controlling method 审中-公开
    半导体存储器件和刷新周期控制方法

    公开(公告)号：US20090193301A1

    公开(公告)日：2009-07-30

    申请号：US12318840

    申请日：2009-01-09

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： H03M13/05 ,  G06F11/00 ,  G06F11/07

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

    摘要翻译： 公开了一种包括错误率测量电路和控制电路的存储器件。 携带BIST电路的误差率测量电路每刷新周期读出并写入用于监视位的区域的数据，以检测刷新周期的错误率（错误计数）。 控制电路进行用于延长和缩短刷新周期的控制，从而实现期望的误码率。 BIST电路发出内部命令和内部地址，并从内部驱动DRAM。 BIST电路写入和读出所需的数据，将监视位与预期值进行比较（错误判定），并对错误进行计数。

    MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION
    85.
    发明申请
    MEMORY APPARATUS AND METHOD USING ERASURE ERROR CORRECTION TO REDUCE POWER CONSUMPTION 有权
    使用擦除误差校正降低功耗的存储器和方法

    公开(公告)号：US20090183053A1

    公开(公告)日：2009-07-16

    申请号：US12014598

    申请日：2008-01-15

    申请人： Yutaka Ito ,  Adrian J. Drexler

    发明人： Yutaka Ito ,  Adrian J. Drexler

    IPC分类号： G11C29/00

    CPC分类号： G11C7/1006 ,  G06F11/106 ,  G11C11/4096 ,  G11C2207/104

    摘要： An error correction circuit coupled to a plurality of memory cells in a memory device includes an error correcting code (“ECC”) generator and an ECC controller. The ECC generator is coupled to the memory cells and recognizes data bits stored in the memory cells as a plurality of data bit strings in a first direction and as a plurality of data bit strings in a second direction such that each data bit string in the first direction and each data bit string in the second direction share one data bit in common. The ECC generator generates a respective correction code in the first direction for each data bit string in the first direction and also generates a respective correction code in the second direction for each data bit string in the second direction. The ECC controller is coupled to the memory cells and the ECC generator. The ECC controller identifies a data bit string in the first direction having more than one data bit in error based on the respective correction code in the first direction and identifies a data bit string in the second direction having more than one data bit in error based on the respective correction code in the second direction. The ECC controller causes the data bit shared by the identified data bit string in the first direction and the identified data bit string in the second direction to be changed from a respective existing value to a respective new value different than the respective existing value.

    摘要翻译： 耦合到存储器件中的多个存储器单元的纠错电路包括纠错码（“ECC”）发生器和ECC控制器。 ECC产生器耦合到存储器单元，并将存储在存储单元中的数据位识别为第一方向上的多个数据位串，并将第二方向上的多个数据位串识别为第一数据位串 方向和第二方向上的每个数据位串共享一个数据位。 ECC发生器在第一方向为每个数据比特串生成在第一方向上的相应校正码，并且在第二方向上为每个数据比特串生成针对第二方向的相应校正码。 ECC控制器耦合到存储器单元和ECC发生器。 ECC控制器基于第一方向上的相应校正码来识别具有多于一个错误数据位的第一方向上的数据位串，并且基于第二方向识别具有错误的多于一个数据位的数据位串，基于 相应的校正码在第二方向上。 ECC控制器使识别的数据位串在第一方向上共享的数据位和第二方向上识别的数据位串从相应的现有值改变为与各自的现有值不同的相应的新值。

    BEAM SPLITTER FOR A LASER MARKING DEVICE
    86.
    发明申请
    BEAM SPLITTER FOR A LASER MARKING DEVICE 有权
    用于激光标记装置的光束分离器

    公开(公告)号：US20090147369A1

    公开(公告)日：2009-06-11

    申请号：US11914251

    申请日：2006-05-12

    申请人： Kazunori Matsushita ,  Takashi Nishimura ,  Noritaka Tadano ,  Yutaka Ito

    发明人： Kazunori Matsushita ,  Takashi Nishimura ,  Noritaka Tadano ,  Yutaka Ito

    IPC分类号： G02B27/14

    CPC分类号： G02B27/095 ,  G02B27/0977 ,  G02B27/144 ,  G02B27/145

    摘要： A laser marking device (1) includes a laser light source (24) that emits a laser beam, and a beam splitter (230) receiving the laser beam and allowing a part of the laser beam to be reflected thereat and a remaining part of the laser beam to be transmitted therethorogh. The beam splitter (230) has an unpolarized film (233a, 233b) into which the laser beam is entered to divide the laser beam into a plurality of laser beams that travels in different directions, at a predetermined rate regardless of change of a polarized characteristic of the laser beam.

    摘要翻译： 激光打标装置（1）包括发射激光束的激光光源（24）和接收激光束并使一部分激光束在其上反射的分束器（230），其余部分 激光束被传送到那里。 分束器（230）具有非偏光膜（233a，233b），其中进入激光束以将激光束分成以不同方向行进的多个激光束，以预定的速率与偏振特性的变化无关 的激光束。

    Semiconductor memory device and refresh period controlling method
    87.
    发明授权
    Semiconductor memory device and refresh period controlling method 失效

    公开(公告)号：US07493531B2

    公开(公告)日：2009-02-17

    申请号：US11152762

    申请日：2005-06-15

    申请人： Yutaka Ito ,  Takeshi Hashimoto

    发明人： Yutaka Ito ,  Takeshi Hashimoto

    IPC分类号： G06F11/00 ,  H03M13/00

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4062

    摘要： Disclosed is a memory device including an error rate measurement circuit and a control circuit. The error rate measurement circuit, carrying a BIST circuit, reads out and writes data for an area for monitor bits every refresh period to detect an error rate (error count) with the refresh period. The control circuit performs control for elongating and shortening the refresh period so that a desired error rate will be achieved. The BIST circuit issues an internal command and an internal address and drives the DRAM from inside. The BIST circuit writes and reads out desired data, compares the monitor bits to expected values (error decision) and counts the errors.

    Semiconductor memory device and error correction method thereof
    88.
    发明授权
    Semiconductor memory device and error correction method thereof 失效
    半导体存储器件及其误差校正方法

    公开(公告)号：US07373584B2

    公开(公告)日：2008-05-13

    申请号：US11152386

    申请日：2005-06-15

    申请人： Yutaka Ito ,  Shigeo Takeuchi

    发明人： Yutaka Ito ,  Shigeo Takeuchi

    IPC分类号： G01C29/00

    CPC分类号： G06F11/1044

    摘要： A semiconductor memory device includes a memory array having a data area and a check code area and a refresh control for controlling a refresh operation in a data holding state. The device also includes an operation system for executing an encoding operation for generating the check code using a bit string in the data area and a decoding operation for performing the error detection/correction of the data using the check code. Additionally, the device includes an encode controller for controlling an encode process in which, in a change to the data holding state, a first and second code are written in the check code area. Furthermore, the device includes a decode controller for controlling a decode process in which, at the end of the data holding state, first and second bit error correction based on each code are alternately performed, and the first and the second bit error correction are performed at least twice respectively.

    摘要翻译： 半导体存储器件包括具有数据区和检查码区的存储器阵列和用于控制数据保持状态下的刷新操作的刷新控制。 该装置还包括一个操作系统，用于执行用于使用数据区域中的比特串产生校验码的编码操作和用于使用校验码执行数据的错误检测/校正的解码操作。 另外，该装置包括编码控制器，用于控制编码处理，其中在数据保持状态的改变中，将第一和第二代码写入校验码区域。 此外，该装置包括用于控制解码处理的解码控制器，其中在数据保持状态结束时交替地执行基于每个代码的第一和第二位错误校正，并执行第一和第二位错误校正 至少两次。

    Method and computer-readable medium for deploying characters in a game
    89.
    发明授权
    Method and computer-readable medium for deploying characters in a game 有权
    用于在游戏中部署角色的方法和计算机可读介质

    公开(公告)号：US07300345B2

    公开(公告)日：2007-11-27

    申请号：US10262948

    申请日：2002-10-03

    申请人： Satoshi Mifune ,  Yutaka Ito

    发明人： Satoshi Mifune ,  Yutaka Ito

    IPC分类号： A63F9/24 ,  A63F13/00 ,  G06F17/00 ,  G06F19/00

    CPC分类号： A63F13/828 ,  A63F13/10 ,  A63F13/58 ,  A63F13/63

    摘要： An object of the present invention is to deploy soccer players in optimum positions in a soccer game. As means for achieving this object, a base position and ability parameters of player characters are stored in memory as attribute data. Player character/formation selection means obtain an operating signal from a controller and thereby obtain player character and formation information. Player character deployment means reference the attribute data to determine the optimum positions for the player characters on a soccer field. Game execution means execute the game on the basis of the determined positions.

    摘要翻译： 本发明的目的是在足球比赛中将足球运动员部署在最佳位置。 作为实现该对象的手段，作为属性数据将游戏者角色的基本位置和能力参数存储在存储器中。 玩家角色/形成选择装置从控制器获得操作信号，从而获得玩家角色和形成信息。 玩家角色部署意味着参考属性数据来确定足球场上的玩家角色的最佳位置。 游戏执行意味着在确定的位置的基础上执行游戏。

    Refresh period generating circuit
    90.
    发明申请
    Refresh period generating circuit 有权
    刷新周期发生电路

    公开(公告)号：US20070253271A1

    公开(公告)日：2007-11-01

    申请号：US11822333

    申请日：2007-07-05

    申请人： Yutaka Ito ,  Nobuhiro Odaira

    发明人： Yutaka Ito ,  Nobuhiro Odaira

    IPC分类号： G11C7/04

    CPC分类号： G11C11/406 ,  G11C7/04 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/4065

    摘要： A refresh period generating circuit which generates a refresh period in refreshing a DRAM cell, comprising: an oscillation circuit which oscillates at a frequency with temperature dependence on ambient temperature; a dividing circuit which divides an oscillation output of the oscillation circuit; a temperature detector which detects the ambient temperature; and a selector which switches and selects among division outputs with respective frequencies from the dividing circuit based on an output of the temperature detector, and outputs a signal as a reference of the refresh period. The temperature dependence in the oscillation circuit includes a positive temperature coefficient in a predetermined temperature range, and does not include a positive temperature coefficient out of the predetermined temperature range. The selector switches the division outputs out of the predetermined temperature range.

    摘要翻译： 一种在刷新DRAM单元时产生刷新周期的刷新周期发生电路，包括：振荡电路，其以与环境温度相关的温度依赖的频率振荡; 分频电路，分频振荡电路的振荡输出; 检测环境温度的温度检测器; 以及选择器，其基于温度检测器的输出，以分频电路的分频输出切换选择，并输出作为刷新周期的基准的信号。 振荡电路中的温度依赖性包括在预定温度范围内的正温度系数，并且不包括超出预定温度范围的正温度系数。 选择器将分割输出切换到预定的温度范围之外。