公开(公告)号：US20060197115A1

公开(公告)日：2006-09-07

申请号：US10551702

申请日：2003-04-03

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： H01L29/768

CPC分类号： G11C13/0004 ,  G11C5/02 ,  G11C7/18 ,  G11C13/0007 ,  G11C2211/4013 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/1233

摘要： A phase change memory device has a semiconductor substrate; a plurality of cell arrays stacked above the semiconductor substrate, each cell array having memory cells arranged in a matrix manner for storing resistance values as data that are determined by phase change of the memory cells, bit lines each commonly connecting one ends of plural memory cells arranged along a first direction of the matrix and word lines each commonly connecting the other ends of plural memory cells arranged along a second direction of the matrix; a read/write circuit formed on the semiconductor substrate as underlying the cell arrays for reading and writing data of the cell arrays; first and second vertical wirings disposed outside of first and second boundaries that define a cell layout region of the cell arrays in the first direction to connect the bit lines of the respective cell arrays to the read/write circuit; and third vertical wirings disposed outside of one of third and fourth boundaries that define the cell layout region in the second direction to connect the word lines of the respective cell arrays to the read/write circuit.

摘要翻译： 相变存储器件具有半导体衬底; 多个单元阵列，堆叠在半导体衬底之上，每个单元阵列具有以矩阵方式布置的存储单元，用于存储电阻值，作为通过存储单元的相变确定的数据，各通常连接多个存储单元的一端的位线 沿着矩阵的第一方向布置，每个字线通常连接沿矩阵的第二方向布置的多个存储单元的另一端; 在半导体衬底上形成的用于读取和写入单元阵列数据的单元阵列的读/写电路; 布置在第一和第二边界之外的第一和第二垂直布线，其限定第一方向上的单元阵列的单元布局区域，以将各单元阵列的位线连接到读/写电路; 以及第三垂直布线，其布置在第三和第四边界之一之外，其限定第二方向上的单元布局区域，以将各单元阵列的字线连接到读/写电路。

公开(公告)号：US07085881B2

公开(公告)日：2006-08-01

申请号：US10681184

申请日：2003-10-09

申请人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

发明人： Kenji Tsuchida ,  Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G06F12/02

CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C2207/2281 ,  G11C2207/229

摘要： A semiconductor memory device includes a bit line, a memory cell coupled to the bit line and a word line coupled to the memory cell. A first time between receiving a write command for a write operation in order to write data to the memory cell and the beginning of the write operation is different from a second time between receiving a refresh command for a refresh operation in order to refresh data stored in the memory cell and beginning the write operation.

摘要翻译： 半导体存储器件包括位线，耦合到位线的存储单元和耦合到存储器单元的字线。 为了向存储器单元写入数据和写入操作的开始，接收写入操作的写入命令之间的第一次不同于接收刷新操作的刷新命令之间的第二次，以刷新存储在存储器单元中的数据 存储单元并开始写操作。

公开(公告)号：US07035833B2

公开(公告)日：2006-04-25

申请号：US10315946

申请日：2002-12-11

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06N3/00

CPC分类号： G06N7/043 ,  Y10S706/90

摘要： A system includes a sensor section which receives fuzzy information inputs X containing a plurality of components and converts the plurality of components into a plurality of measurable input physical quantities, a converter which receives a plurality of input physical quantities and converts the input physical quantities into a plurality of pulses having pulse widths corresponding to the magnitudes thereof, and a feature extraction section (NF) which receives a plurality of pulses, selects the plurality of pulses by using a set pulse width as a reference, and extracts feature information items y0, y1, y2, . . . which express the features of the fuzzy information inputs X from the fuzzy information inputs X according to the number of selected pulses.

摘要翻译： 一种系统包括传感器部分，其接收包含多个分量的模糊信息输入X并将多个分量转换成多个可测量的输入物理量;转换器，其接收多个输入物理量并将输入的物理量转换为 具有与其大小对应的脉冲宽度的多个脉冲和接收多个脉冲的特征提取部（NF），通过使用设定脉冲宽度作为基准选择多个脉冲，并且提取特征信息项y 0， y 1，y 2，... 。 。 其根据所选脉冲的数量从模糊信息输入X表达模糊信息输入X的特征。

公开(公告)号：US06847555B2

公开(公告)日：2005-01-25

申请号：US10461398

申请日：2003-06-16

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G11C16/04 ,  G06K19/07 ,  G11C7/06 ,  G11C11/34 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/28 ,  H04N5/907

CPC分类号： G11C7/065 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3459 ,  G11C2211/5621

摘要： A non-volatile semiconductor memory device includes: a memory cell array in which a plurality of electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to write M-value data (where, M is an integer equal to 4 or more) to pair-cells each constituted by simultaneously selected first and second memory cells connected to a pair of bit lines in the memory cell array, the M-value data being defined as a combination of different threshold levels of the first and second memory cells in M threshold levels to be set at each memory cell, and read M-value data stored in each pair-cell by sensing a difference between cell currents of the first and second memory cells; and a controller configured to control data write and read operations for the memory cell array.

摘要翻译： 非挥发性半导体存储器件包括：存储单元阵列，其中布置有多个电可重写和非易失性存储单元; 一个读出放大器电路，被配置为将M值数据（其中，M是等于4或更大的整数）写入到由存储单元阵列中的一对位线连接的同时选择的第一和第二存储器单元构成的配对单元 M值数据被定义为要在每个存储单元设置的M个阈值电平中的第一和第二存储器单元的不同阈值电平的组合，并且通过感测差分来读取存储在每对单元中的M值数据 在第一和第二存储器单元的单元电流之间; 以及控制器，被配置为控制所述存储单元阵列的数据写入和读取操作。

公开(公告)号：US06639869B2

公开(公告)日：2003-10-28

申请号：US10310797

申请日：2002-12-06

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2207/2254

摘要： A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mode setting cycle. In the normal mode, setting of addresses is performed irrespective of a clock signal. In the synchronous mode, an edge of the clock signal determines the timing of operation.

公开(公告)号：US06510101B2

公开(公告)日：2003-01-21

申请号：US09983383

申请日：2001-10-24

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2207/2254

摘要： A semiconductor device includes a memory cell array, a control section and latency setting circuit. The control section configured to receive a clock signal and a first control signal, and configured to output a plurality of the data in synchronism with the clock signal after the first control signal is asserted, output of the data beginning a number of clock cycles (latency N) of the clock signal (latency N being a positive integer ≧2) after the first control signal is asserted, a different one of the data being output at each of the clock cycles after the output begins until the plurality of data is output. The latency setting circuit sets the latency N. The latency setting circuit includes at least one switch which permanently fixes a latency.

公开(公告)号：US06389521B1

公开(公告)日：2002-05-14

申请号：US09655939

申请日：2000-09-06

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F1202

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： An image memory has a random access memory array capable of being randomly accessed; a serial access memory array partitioned into n power of 2 (n>1) divisional areas cyclically and serially accessed in asynchronism with the random access memory; data transfer unit for transferring data between the random access memory array and the serial access memory array; a determined unit for determining a row of data to be transferred from the random access memory array to each of the divisional areas; and a designating unit for designating at least one of a top serial access address and a last serial access address respectively of each divisional area, wherein the data transfer unit executes data transfer from the random access memory array to the serial access memory array in accordance with outputs from the determining unit and the designating unit.

摘要翻译： 图像存储器具有随机访问的随机存取存储器阵列; 串行访问存储器阵列，其被循环地和随机存取存储器不同步地循环地和串行访问地分成2（n> 1）个分区的n个功率; 数据传送单元，用于在随机存取存储器阵列和串行存取存储器阵列之间传送数据; 确定单元，用于确定要从所述随机存取存储器阵列传送到每个所述分区的数据行; 以及指定单元，用于分别指定每个分区的顶部串行访问地址和最后一个串行访问地址中的至少一个，其中数据传送单元执行从随机存取存储器阵列到串行访问存储器阵列的数据传送，根据 来自确定单元和指定单元的输出。

公开(公告)号：US06335904B1

公开(公告)日：2002-01-01

申请号：US09852037

申请日：2001-05-10

申请人： Kenji Tsuchida ,  Haruki Toda

发明人： Kenji Tsuchida ,  Haruki Toda

IPC分类号： G11C800

CPC分类号： G11C11/4094 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/002

摘要： In a semiconductor memory system, an SDRAM comprises a memory cell array 101 which is divided into a plurality of cell array blocks, a column decoder, a row decoder, and a sense amplifier circuit. In the SDRAM, a first operation mode with a first cycle time is set when successive access within a cell array block is conducted, a second operation mode with a second cycle time shorter than the first cycle time is set when successive access covering the cell array blocks being apart from each other is conducted and a third operation mode with a medium cycle time is set when successive access covering the cell array blocks adjacent to each other is conducted. With the above constitution, a high speed access can be realized without provision of a specific accessory circuit while suppressing overhead for a semiconductor chip size.

摘要翻译： 在半导体存储器系统中，SDRAM包括被分成多个单元阵列块的存储单元阵列101，列解码器，行解码器和读出放大器电路。 在SDRAM中，当进行单元阵列块中的连续访问时，设置具有第一周期时间的第一操作模式，当覆盖单元阵列的连续访问时，设置具有比第一周期时间短的第二周期时间的第二操作模式 进行彼此分开的块，并且进行覆盖彼此相邻的单元阵列块的连续访问时，设定具有中等周期时间的第三操作模式。 利用上述结构，可以在不设置特定附件电路的同时抑制半导体芯片尺寸的开销，实现高速访问。

公开(公告)号：US06321343B1

公开(公告)日：2001-11-20

申请号：US09698635

申请日：2000-10-27

申请人： Haruki Toda

发明人： Haruki Toda

IPC分类号： G06F104

CPC分类号： G11C7/1093 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/225

摘要： A maximum flight time measuring circuit constituted by a first delay circuit for delaying a system clock and controlling its delay time in accordance with a strobe clock from DIMMs and a delayline register circuit for storing a delayed state in the delay circuit, and a second delay circuit are provided. Contents of the delayline register circuit are input to the second delay circuit, which is controlled to generate the same delay as that of the first delay circuit. The output of the second delay circuit is supplied as a data fetch signal to a control buffer for receiving read data DQ from the DIMMs.

摘要翻译： 一种最大飞行时间测量电路，由第一延迟电路构成，用于根据来自DIMM的选通时钟延迟系统时钟并控制其延迟时间;以及延迟线寄存器电路，用于在延迟电路中存储延迟状态;以及第二延迟电路 被提供。 延迟线寄存器电路的内容被输入到第二延迟电路，其被控制以产生与第一延迟电路相同的延迟。 第二延迟电路的输出作为数据提取信号提供给用于从DIMM接收读取数据DQ的控制缓冲器。

公开(公告)号：US06310821B1

公开(公告)日：2001-10-30

申请号：US09435627

申请日：1999-11-08

申请人： Haruki Toda ,  Hitoshi Kuyama

发明人： Haruki Toda ,  Hitoshi Kuyama

IPC分类号： G11C800

CPC分类号： G11C8/04 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/50016 ,  G11C2207/2254

摘要： A clock-synchronous semiconductor memory device includes many memory cells arranged in matrix, a count section for counting the actual number of cycles of a continuous, externally-supplied basic clock signal, a control section for inputting a row enable control signal (/RE) and the column enable control signal (/CE) provided from an external device, other than the basic clock signal, for which the control signals are at a specified level, synchronized with the basic control signal, and for setting the initial address for data access of the memory cells, and a data I/O section for executing a data access operation for the address set by the control section. In the device, the output of data from the memory cells through the data I/O means is started after the setting of the initial address by the control sections and after a specified number of basic clock signals has been counted by the count section.

摘要翻译： 时钟同步半导体存储器件包括以矩阵形式布置的许多存储器单元，用于对连续的外部供给的基本时钟信号的实际循环次数进行计数的计数部分，用于输入行使能控制信号（/ RE）的控制部分， 以及与基本时钟信号不同的外部设备提供的与基本控制信号同步的指令级别的列使能控制信号（/ CE），并且用于设置用于数据访问的初始地址 以及用于执行由控制部分设置的地址的数据访问操作的数据I / O部分。 在该设备中，通过控制部分设置初始地址之后并且在计数部分计数了指定数量的基本时钟信号之后，通过数据I / O装置从存储器单元输出数据。