公开(公告)号：US07288804B2

公开(公告)日：2007-10-30

申请号：US11372380

申请日：2006-03-09

申请人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

发明人： Roger A. Booth, Jr. ,  Kangguo Cheng ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L27/10

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrically programmable fuse structures for an integrated circuit and methods of fabrication thereof are presented, wherein the electrically programmable fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The first terminal portion and the second terminal portion reside over a first support and a second support, respectively, with the first support and the second support being spaced apart, and the fuse element bridging the distance between the first terminal portion over the first support and the second terminal portion over the second support. The fuse, first support and second support define a α-shaped structure in elevational cross-section through the fuse element. The first terminal portion, second terminal portion and fuse element are coplanar, with the fuse element residing above a void, which in one embodiment is filed by a thermally insulating dielectric material that surrounds the fuse element.

摘要翻译： 提出了用于集成电路的电可编程熔丝结构及其制造方法，其中电可编程熔丝具有由熔丝元件互连的第一端子部分和第二端子部分。 第一端子部分和第二端子部分分别驻留在第一支撑件和第二支撑件上，第一支撑件和第二支撑件间隔开，并且熔丝元件将第一端子部分之间的距离跨越第一支撑件和 在第二支撑件上方的第二端子部分。 保险丝，第一支撑件和第二支撑件在通过熔断元件的正面横截面中限定了α形结构。 第一端子部分，第二端子部分和熔丝元件是共面的，其中熔丝元件位于空隙上方，在一个实施例中，熔断元件由围绕熔丝元件的绝热介电材料覆盖。

公开(公告)号：US07226816B2

公开(公告)日：2007-06-05

申请号：US11055106

申请日：2005-02-11

申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L21/82

CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.

摘要翻译： 可以在低电压和电流下被编程并且潜在地消耗很少的芯片空间并且可以间隙地在间隔最小光刻特征尺寸的元件之间形成的抗熔丝结构形成在复合衬底上，例如绝缘体上硅 通过蚀刻通过绝缘体的接触到支撑半导体层，优选结合形成到达或支撑层的电容器状结构。 反熔丝可以由导体形成的选定位置和/或损坏电容器状结构的电介质来编程。 绝缘环用于围绕导体或电容器状结构的一部分，以将损伤限制在所需位置。 由于编程电流导致的加热效应电压和噪声被有效地隔离到体硅层，从而允许在器件正常工作期间进行编程。 因此实现了自动修复而不中断操作的可能性。

公开(公告)号：US06674139B2

公开(公告)日：2004-01-06

申请号：US09910636

申请日：2001-07-20

申请人： Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

发明人： Jack A. Mandelman ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L2976

CPC分类号： H01L29/4983 ,  H01L21/28061 ,  H01L21/28114 ,  H01L29/42368 ,  H01L29/66492 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/66583 ,  H01L29/66598 ,  H01L29/66666

摘要： A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.

摘要翻译： 场效应晶体管具有具有较厚中心部分和较薄翼的逆T栅极导体。 翼可以是与中心部分不同的材料。 此外，栅极电介质可以沿着边缘比在中心更厚。 翅膀下的掺杂也可以不同于沿着中心部分或超出门。 机翼下方的区域可能与栅极导体的掺杂不同。 利用基本上垂直的注入，在不注入沟道的中心部分的情况下注入与栅极的边缘重叠的沟道的区域，并且阻止该区域接收栅电极的所接收的较厚部分的至少一部分 。

公开(公告)号：US06674134B2

公开(公告)日：2004-01-06

申请号：US09173430

申请日：1998-10-15

申请人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

发明人： Wayne S. Berry ,  Jeffrey P. Gambino ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L2976

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823462

摘要： The present invention provides an integrated circuit which comprises a substrate having a plurality of device regions formed therein, said plurality of device regions being electrically isolated from each other by shallow trench isolation (STI) regions and said plurality of device regions each having opposing edges abutting its corresponding STI region; selected ones of said devices regions having a preselected first device width such that an oxide layer formed thereon includes substantially thicker perimeter regions, along said opposing edges, compared to a thinner central region that does not abut its corresponding STI region; and selected other ones of the device regions having a preselected device width substantially narrower in width than the first device width such that an oxide layer formed thereon includes perimeter regions, along opposing edges, that abut each other over its central region thereby preventing formation of a corresponding thinner central region.

摘要翻译： 本发明提供一种集成电路，其包括其中形成有多个器件区的衬底，所述多个器件区通过浅沟槽隔离（STI）区域彼此电隔离，并且所述多个器件区域各自具有相对的边缘邻接 其对应的STI区域; 所选择的所述器件区域具有预先选择的第一器件宽度，使得形成在其上的氧化物层与不相邻其对应的STI区的较薄的中心区域相比，沿着所述相对的边缘包括基本上较厚的周边区域; 以及选定的其它器件区域具有基本上比第一器件宽度窄的宽度的预选器件宽度，使得形成在其上的氧化物层包括沿相对边缘的周边区域，该周边区域在其中心区域上彼此邻接，从而防止形成 相应较薄的中心区域。

公开(公告)号：US06635543B2

公开(公告)日：2003-10-21

申请号：US10335652

申请日：2002-12-31

申请人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

发明人： Toshiharu Furukawa ,  Jack A. Mandelman ,  Dan Moy ,  Byeongju Park ,  William R. Tonti

IPC分类号： A01L21331

CPC分类号： H01L27/10894 ,  H01L21/76262 ,  H01L21/76264 ,  H01L21/76278 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/1207

摘要： A method and structure for selectively growing epitaxial silicon in a trench formed within a silicon-on-insulator (SOI) structure. The SOI structure includes a buried oxide layer (BOX) on a bulk silicon substrate, and a silicon layer on the BOX. A pad layer is formed on the silicon layer. The pad layer includes a pad nitride (e.g., silicon nitride) on a pad oxide (e.g., silicon dioxide), and the pad oxide has been formed on the silicon layer. A trench is formed by anisotropically etching through the pad layer, the silicon layer, the BOX, and to a depth within the bulk silicon substrate. Insulative spacers are formed on sidewalls of the trench. An epitaxial silicon layer is grown in the trench from a bottom of the trench to above the pad layer. The pad layer and portions of the epitaxial layer are removed (e.g., by chemical mechanical polishing), resulting in a planarized top surface of the epitaxial layer that is about coplanar with a top surface of the silicon layer. Electronic devices may be formed within the epitaxial silicon of the trench. Such electronic devices may include dynamic random access memory (DRAM), bipolar transistors, Complementary Metal Oxide Semiconductor (CMOS) circuits which are sensitive to floating body effects, and devices requiring threshold voltage matching. Semiconductor devices (e.g., field effect transistors) may be coupled to the SOI structure outside the trench.

摘要翻译： 一种用于在形成于绝缘体上硅（SOI）结构中的沟槽中选择性地生长外延硅的方法和结构。 SOI结构包括在体硅衬底上的掩埋氧化物层（BOX）和BOX上的硅层。 衬垫层形成在硅层上。 焊盘层包括衬垫氧化物（例如，二氧化硅）上的衬垫氮化物（例如，氮化硅），并且衬垫氧化物已经形成在硅层上。 通过各向异性地蚀刻通过焊盘层，硅层，BOX以及体硅衬底内的深度形成沟槽。 绝缘垫片形成在沟槽的侧壁上。 在沟槽中从沟槽的底部到焊盘层的上方生长外延硅层。 去除衬垫层和外延层的部分（例如，通过化学机械抛光），导致外延层的平坦化顶表面与硅层的顶表面大致共面。 电子器件可以形成在沟槽的外延硅内。 这样的电子设备可以包括对浮体效应敏感的动态随机存取存储器（DRAM），双极晶体管，互补金属氧化物半导体（CMOS）电路以及需要阈值电压匹配的器件。 半导体器件（例如，场效应晶体管）可以耦合到沟槽外部的SOI结构。

公开(公告)号：US06544837B1

公开(公告)日：2003-04-08

申请号：US09527743

申请日：2000-03-17

申请人： Ramachandra Divakauni ,  Mark C. Hakey ,  William H.-L. Ma ,  Jack A. Mandelman ,  William R. Tonti

发明人： Ramachandra Divakauni ,  Mark C. Hakey ,  William H.-L. Ma ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L2146

CPC分类号： H01L27/10867 ,  H01L22/32 ,  H01L23/481 ,  H01L23/535 ,  H01L27/10832 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S977/712 ,  Y10S977/721 ,  Y10S977/779 ,  Y10S977/90 ,  Y10S977/94 ,  H01L2924/00

摘要： A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

摘要翻译： 通过在晶片上粘合绝缘体层而形成的复合层状集成电路提供了诸如沟槽电容器DRAM阵列和高性能，低功率，低电压绝缘体上硅（SOI）开关晶体管和短信号传播路径之类的不相容技术的组合 在形成在芯片的各个晶片层上的器件之间。 在优选实施例中，通过在集成电路器件上的晶片亲水键合然后使用注入的氢和低温热处理将第二晶片的层切割掉，形成SOI晶片。 各种结构和组合物的其它晶片可以在其上结合，并且使用提供快速信号传播的短通孔制成的各个晶片中的电路元件和连接焊盘之间的连接以及提供比在芯片边缘上提供更多的连接。

公开(公告)号：US06498518B1

公开(公告)日：2002-12-24

申请号：US09617680

申请日：2000-07-14

申请人： Russell J. Houghton ,  Jack A. Mandelman ,  Azzouz Nezar ,  Wilbur D. Pricer ,  William R. Tonti

发明人： Russell J. Houghton ,  Jack A. Mandelman ,  Azzouz Nezar ,  Wilbur D. Pricer ,  William R. Tonti

IPC分类号： H03K522

CPC分类号： H04L25/0292 ,  H03K5/24 ,  H03K19/017554

摘要： A current sensing circuit connected to a power supply terminal and having at least one input terminal and at least one output terminal includes at least one bipolar transistor having a base, emitter and collector, at least one current mirror amplifier connected to the power supply terminal, the current mirror amplifier having an input connected to the collector and having at least one output connected to the emitter, and a DC voltage source connected to the base.

摘要翻译： 连接到电源端子并且具有至少一个输入端子和至少一个输出端子的电流感测电路包括至少一个具有基极，发射极和集电极的双极晶体管，连接到电源端子的至少一个电流镜放大器， 所述电流镜放大器具有连接到所述集电极并且具有连接到所述发射极的至少一个输出的输入端和连接到所述基极的DC电压源。

公开(公告)号：US06492211B1

公开(公告)日：2002-12-10

申请号：US09656819

申请日：2000-09-07

申请人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

发明人： Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  W. David Pricer ,  William R. Tonti

IPC分类号： H01L2100

CPC分类号： H01L27/10894 ,  G11C7/065 ,  G11C2207/005 ,  G11C2207/065 ,  H01L21/84 ,  H01L27/10861 ,  H01L27/10897 ,  H01L27/1203

摘要： There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PNP device is implemented by changing the array transistor to a PFET. Particularly, a BICMOS device is fabricated in SOI. The bipolar emitter contacts and CMOS diffusion contacts are formed simultaneously of polysilicon plugs. The CMOS diffusion contact is the plug contact from bitline to storage node of a memory cell.

摘要翻译： 在此公开了独特的制造顺序和集成到典型的DRAM沟槽工艺序列中的垂直绝缘体上硅（SOI）双极晶体管的结构。 使用NFET的DRAM阵列允许集成双极NPN序列。 类似地，通过将​​阵列晶体管改变为PFET来实现垂直双极PNP器件。 特别地，在SOI中制造BICMOS器件。 双极发射极触点和CMOS扩散触点同时形成多晶硅插头。 CMOS扩散触点是从存储单元的位线到存储节点的插头触点。

公开(公告)号：US06436749B1

公开(公告)日：2002-08-20

申请号：US09658655

申请日：2000-09-08

申请人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

发明人： William R. Tonti ,  Claude L. Bertin ,  Jeffrey P. Gambino ,  Russell J. Houghton ,  Jack A. Mandelman ,  Wilbur D. Pricer

IPC分类号： H01L218238

CPC分类号： H01L27/092 ,  H01L21/823842

摘要： A method for forming mixed high voltage/low voltage (HV/LV) transistors for CMOS devices is disclosed. In an exemplary embodiment, depletion of the gate conductor is controlled by leaving a fixed region of the gate conductor intrinsic, or lightly doped, thus separating the heavily doped low resistivity portion of the electrode with an intrinsic region by use of a conducting dopant barrier. The barrier is conductive in nature, but acts as a well-controlled diffusion barrier, stopping the “fast” diffusion which normally takes place in polysilicon, and eliminating diffusion between the conductors. Thereby, the device performance may be precisely predicted by carefully controlling the gate conductor thickness.

摘要翻译： 公开了一种用于形成用于CMOS器件的混合高压/低压（HV / LV）晶体管的方法。 在示例性实施例中，通过将栅极导体的固定区域固有或轻掺杂来控制栅极导体的耗尽，从而通过使用导电掺杂剂屏障将本征区域的重掺杂低电阻率部分与本征区域分离。 阻挡层本质上是导电的，但是作为良好控制的扩散屏障，停止通常在多晶硅中发生的“快速”扩散，并消除导体之间的扩散。 因此，可以通过仔细地控制栅极导体厚度来精确地预测器件性能。

公开(公告)号：US06396121B1

公开(公告)日：2002-05-28

申请号：US09583468

申请日：2000-05-31

申请人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

发明人： Claude L. Bertin ,  Ramachandra Divakaruni ,  Russell J. Houghton ,  Jack A. Mandelman ,  William R. Tonti

IPC分类号： H01L2900

CPC分类号： H01L23/5252 ,  H01L27/10829 ,  H01L27/10897 ,  H01L27/1203 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device. Thus the potential for self-repair without interruption of operation is realized.