公开(公告)号：US07755137B2

公开(公告)日：2010-07-13

申请号：US11245995

申请日：2005-10-07

申请人： Gary Dolny ,  Qi Wang

发明人： Gary Dolny ,  Qi Wang

IPC分类号： H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7782 ,  Y02P70/605

摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A body tie on this device can also be eliminated to reduce transistor cell size. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Device characteristics are also improved. For example, parasitic gate impedance is reduced through the use of a poly SiGe gate, and channel resistance is reduced through the use of a SiGe layer near the device's gate.

摘要翻译： 提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。 提高对松开感应开关事件的抗扰度。 例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。 也可以消除该器件上的身体接合以减少晶体管电池尺寸。 还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。 当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。 设备特性也得到改善。 例如，通过使用多晶硅栅极减少寄生栅极阻抗，并且通过在器件栅极附近使用SiGe层来减小沟道电阻。

公开(公告)号：US20100118899A1

公开(公告)日：2010-05-13

申请号：US12268203

申请日：2008-11-10

申请人： Xiaoyuan Peng ,  David Barsic ,  William J. Jordens ,  Qi Wang

发明人： Xiaoyuan Peng ,  David Barsic ,  William J. Jordens ,  Qi Wang

IPC分类号： H01S3/10

CPC分类号： H01S3/06754 ,  H01S3/2316 ,  H01S3/2383 ,  H01S5/005 ,  H01S5/0092 ,  H01S5/0428 ,  H01S5/12

摘要： A programmable laser pulse combines electrical modulation of the pulse frequency and optical modulation of the pulse shape to form laser pulses of prescribed pulse shapes. A prescribed pulse shape features high peak power and low average power. The laser system disclosed also allows for power-scaling and nonlinear conversions to other (shorter or longer) wavelengths. The system provides an economical reliable alternative to using a laser source with high repetition rates to achieve shaped pulses at a variety of wavelengths. The combinatorial scheme disclosed is inherently more efficient than existing subtractive methods.

摘要翻译： 可编程激光脉冲组合脉冲频率的电调制和脉冲形状的光调制形成规定脉冲形状的激光脉冲。 规定的脉冲形状具有高峰值功率和低平均功率。 所公开的激光系统还允许对其它（更短或更长）波长进行功率缩放和非线性转换。 该系统提供了使用具有高重复率的激光源实现各种波长的成形脉冲的经济可靠的替代方案。 所公开的组合方案固有地比现有的减法方法更有效。

公开(公告)号：US20100109129A1

公开(公告)日：2010-05-06

申请号：US12262570

申请日：2008-10-31

申请人： Yong Liu ,  Qi Wang

发明人： Yong Liu ,  Qi Wang

IPC分类号： H01L23/50 ,  H01L21/60

CPC分类号： H01L23/481 ,  H01L21/6836 ,  H01L21/76898 ,  H01L24/83 ,  H01L25/074 ,  H01L2221/68327 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/83851 ,  H01L2924/00011 ,  H01L2924/01079 ,  H01L2924/13091 ,  H02M3/155 ,  H01L2224/29075 ,  H01L2924/00014

摘要： A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front side of the LS die, the LS die having source, drain, and gate bonding pads located on a front side of a second section separate from the first section, the drain bonding pad electrically connected to the back side of the LS die in the second section. The HS die and the LS die are bonded together such that the source bonding pad of the HS die is electrically connected to the back side of the LS die, and each of the drain and gate bonding pads are electrically connected to separate TSVs in the LS die.

摘要翻译： 降压转换器模块包括在HS模头的正面上具有源极，漏极和栅极接合焊盘的高侧（HS）裸片，具有第一部分的多个通孔硅通孔的低侧（LS）裸片 TSV），所述LS模具具有位于与所述第一部分分离的第二部分的前侧上的源极，漏极和栅极接合焊盘，所述漏极接合焊盘电连接到 第二部分LS模具的背面。 HS管芯和LS管芯结合在一起，使得HS管芯的源极焊盘电连接到LS管芯的背面，并且漏极和栅极焊盘中的每一个电连接到LS中的分离TSV 死。

公开(公告)号：US07710791B2

公开(公告)日：2010-05-04

申请号：US11984145

申请日：2007-11-14

申请人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

发明人： Kwang-jin Lee ,  Won-Seok Lee ,  Qi Wang ,  Hye-Jin Kim ,  Joon Yong Choi

IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C7/22 ,  G11C8/18

CPC分类号： G11C7/1078 ,  G11C7/1084 ,  G11C7/225 ,  G11C16/10

摘要： A non-volatile semiconductor memory device may include a memory cell array that may include a plurality of memory transistors; a input circuit that may control a voltage level of an internal reference voltage and a delay time of an internal clock signal in response to an MRS trim code or an electric fuse trim code, and that may generate a first buffered input signal; a column gate that may gate the first buffered input signal in response to a decoded column address signal; and a sense amplifier that may amplify an output signal of the memory cell array to output to the column gate, and that may receive an output signal of the column gate to output to the memory cell array. The non-volatile semiconductor memory device may properly buffer an input signal of a small swing range.

摘要翻译： 非易失性半导体存储器件可以包括可以包括多个存储晶体管的存储单元阵列; 输入电路，其可以响应于MRS修剪代码或电熔丝修剪代码来控制内部参考电压的电压电平和内部时钟信号的延迟时间，并且可以产生第一缓冲输入信号; 列门，其可以响应于解码列地址信号而选通第一缓冲输入信号; 以及读出放大器，其可以放大存储单元阵列的输出信号以输出到列门，并且可以接收列门的输出信号以输出到存储器单元阵列。 非易失性半导体存储器件可以适当地缓冲小摆动范围的输入信号。

公开(公告)号：US07653885B2

公开(公告)日：2010-01-26

申请号：US11746026

申请日：2007-05-08

申请人： Sourav Nandy ,  Qi Wang

发明人： Sourav Nandy ,  Qi Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

摘要翻译： 提供了一种方法，用于从单元库内的多个电路单元中选择用于集成电路设计的优化中使用的电路单元，该方法包括：获得表示单元电力的多个单元的值 耗散和电池输出电压变化率; 基于这些值对多个单元进行排序; 识别在满足阈值的单元的排序内彼此相邻的单元格的值之间的差异; 并且基于所识别的差异来指定小区的排序中的切点。

公开(公告)号：US07629455B2

公开(公告)日：2009-12-08

申请号：US11765504

申请日：2007-06-20

申请人： Donald E. Nelson ,  Brendan S. Hinchey ,  Michelle Lacy ,  James A. Morrell ,  Andrey A. Boukharov ,  Zhaolong Li ,  Wei Wu ,  Linda Lutfiyya ,  Maolong Lu ,  David K. Kovalic ,  Qi Wang ,  Ping Li ,  Yongwei Cao

发明人： Donald E. Nelson ,  Brendan S. Hinchey ,  Michelle Lacy ,  James A. Morrell ,  Andrey A. Boukharov ,  Zhaolong Li ,  Wei Wu ,  Linda Lutfiyya ,  Maolong Lu ,  David K. Kovalic ,  Qi Wang ,  Ping Li ,  Yongwei Cao

IPC分类号： C07H21/04 ,  A01H5/00 ,  C12N15/82

CPC分类号： C12N15/8222 ,  C12N15/8223 ,  C12N15/823

摘要： The present invention provides non-coding regulatory element polynucleotide molecules isolated from the transcription factor Nuclear Factor B (NFB2) gene of Zea mays and useful for expressing transgenes in plants. The invention further discloses compositions, polynucleotide constructs, transformed host cells, transgenic plants and seeds containing the Zea mays NFB2 regulatory polynucleotide sequences, and methods for preparing and using the same.

摘要翻译： 本发明提供从玉米的转录因子核因子B（NFB2）基因分离的非编码调节元件多核苷酸分子，并且可用于在植物中表达转基因。 本发明进一步公开了组合物，多核苷酸构建体，转化的宿主细胞，转基因植物和含有Zea mays NFB2调控多核苷酸序列的种子，以及制备和使用它们的方法。

公开(公告)号：US20090269896A1

公开(公告)日：2009-10-29

申请号：US12109302

申请日：2008-04-24

申请人： Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

发明人： Hui Chen ,  Qi Wang ,  Briant Harward ,  James Pan

IPC分类号： H01L21/336

CPC分类号： H01L21/3065 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/7827

摘要： A method for forming a semiconductor structure includes the following steps. Trenches are formed in a semiconductor region using a masking layer such that the trenches have a first depth, a first width along their bottom, and sidewalls having a first slope. The masking layer is removed, and a bevel etch is performed to taper the sidewalls of the trenches so that the sidewalls have a second slope less than the first slope.

摘要翻译： 一种形成半导体结构的方法包括以下步骤。 在半导体区域中使用掩模层形成沟槽，使得沟槽具有第一深度，沿其底部的第一宽度和具有第一斜率的侧壁。 去除掩模层，并且执行斜面蚀刻以使沟槽的侧壁逐渐变细，使得侧壁具有小于第一斜率的第二斜率。

公开(公告)号：US20090181520A1

公开(公告)日：2009-07-16

申请号：US12174863

申请日：2008-07-17

申请人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

发明人： Minhua Li ,  Qi Wang ,  Gordon Sim ,  Matthew Reynolds ,  Suku Kim ,  James J. Murphy ,  Hamza Yilmaz

IPC分类号： H01L21/78

CPC分类号： H01L21/78

摘要： A method for obtaining individual dies from a semiconductor structure is disclosed. The semiconductor structure includes a device layer, and the device layer in turn includes active regions separated by predefined spacings. Thick metal is selectively formed on backside of the device layer such that thick metal is formed on backside of active regions but not on backside of the predefined spacings. The semiconductor structure is then cut along the predefined spacings to separate the active regions with thick metal on their backside into individual dies.

摘要翻译： 公开了一种从半导体结构获得单个管芯的方法。 半导体结构包括器件层，器件层又包括由预定间隔隔开的有源区。 在器件层的背侧选择性地形成厚金属，使得在有源区的背面形成厚金属，而不在预定间隔的背面形成厚金属。 然后沿着预定的间隔切割半导体结构，以将其背面的厚金属的活性区域分离成单独的管芯。

公开(公告)号：US20090070054A1

公开(公告)日：2009-03-12

申请号：US11965630

申请日：2007-12-27

申请人： Lingbo Zeng ,  Dazhi Teng ,  Saixin Zhou ,  Lin Tan ,  Qi Wang

发明人： Lingbo Zeng ,  Dazhi Teng ,  Saixin Zhou ,  Lin Tan ,  Qi Wang

IPC分类号： G06F19/00

CPC分类号： A61B5/7275 ,  A61B5/024 ,  A61B5/044 ,  A61B5/145 ,  A61B5/743 ,  A61B5/7435 ,  G06F19/00 ,  G16H40/63

摘要： A method and an apparatus are provided for performing waveform analysis on physiological parameters. In one embodiment, a method includes reading measurement values of a first physiological parameter relating to time, and displaying them as a trend display graph in a trend display area that includes first coordinates representing time and second coordinates representing the measurement values. The method also includes acquiring a time selected in the trend display graph, and displaying, in a waveform display area, waveform data of a second physiological parameter associated with formation of the first physiological parameter during periods before and after the selected time. The waveform display area includes time coordinates. The disclosed embodiments allow medical staff to view the curve of a patient's physiological parameters throughout a monitoring/therapy period. Medical staff may make a detailed analysis of the waveform data in real time, which may provide a basis for making decisions in the following therapy processes.

摘要翻译： 提供了一种用于对生理参数进行波形分析的方法和装置。 在一个实施例中，一种方法包括读取与时间相关的第一生理参数的测量值，并且在趋势显示区域中显示它们作为趋势显示图，其包括表示表示测量值的时间和第二坐标的第一坐标。 该方法还包括获取在趋势显示图中选择的时间，并且在波形显示区域中，在所选择的时间之前和之后的周期期间，显示与形成第一生理参数相关联的第二生理参数的波形数据。 波形显示区域包括时间坐标。 所公开的实施例允许医务人员在整个监测/治疗期间观察患者生理参数的曲线。 医务人员可以实时对波形数据进行详细分析，为以后治疗过程中的决策提供依据。

公开(公告)号：US20080189662A1

公开(公告)日：2008-08-07

申请号：US11746026

申请日：2007-05-08

申请人： Sourav NANDY ,  Qi Wang

发明人： Sourav NANDY ,  Qi Wang

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/78

摘要： A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

摘要翻译： 提供了一种方法，用于从单元库内的多个电路单元中选择用于集成电路设计的优化中使用的电路单元，该方法包括：获得表示单元电力的多个单元的值 耗散和电池输出电压变化率; 基于这些值对多个单元进行排序; 识别在满足阈值的单元的排序内彼此相邻的单元格的值之间的差异; 并且基于所识别的差异来指定小区的排序中的切点。