公开(公告)号：US20060133153A1

公开(公告)日：2006-06-22

申请号：US11016666

申请日：2004-12-17

申请人： Yen-Hao Shih ,  Hang-Ting Lue

发明人： Yen-Hao Shih ,  Hang-Ting Lue

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0466 ,  G11C16/3418

摘要： A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the transistor control gate. In another embodiment, the method further comprises performing a baking process on the memory device. The method further comprises performing a memory operation on the memory device.

摘要翻译： 稳定存储器件的方法包括在存储器件的电荷俘获层中俘获多个电荷。 电荷捕获层位于晶体管控制栅极和晶体管沟道区域之间。 该方法还包括向晶体管控制栅极施加负电压偏置。 在另一个实施例中，该方法还包括在存储器件上执行烘焙处理。 该方法还包括对存储器设备执行存储器操作。

公开(公告)号：US08987098B2

公开(公告)日：2015-03-24

申请号：US13527259

申请日：2012-06-19

申请人： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

发明人： Shih-Hung Chen ,  Yen-Hao Shih ,  Hang-Ting Lue

IPC分类号： H01L21/336 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/11565

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Partly oxidized lines of material such as silicon are made over a plurality of stacked nonvolatile memory structures. Word line trenches are made in the partly oxidized lines, by removing the unoxidized lines from the intermediate parts of the partly oxidized lines, leaving the plurality of oxidized lines at the outer parts of the plurality of partly oxidized lines. Word lines are made in the word line trenches over the plurality of stacked nonvolatile memory structures.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 在多个堆叠的非易失性存储器结构上制造部分氧化的材料线如硅。 通过从部分氧化的线的中间部分去除未氧化的线，在多个部分氧化的线的外部部分留下多条氧化线，在部分氧化的线中形成字线沟槽。 在多个堆叠的非易失性存储器结构中的字线沟槽中形成字线。

公开(公告)号：US08759899B1

公开(公告)日：2014-06-24

申请号：US13739914

申请日：2013-01-11

申请人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

发明人： Hang-Ting Lue ,  Yi-Hsuan Hsiao ,  Shih-Hung Chen ,  Yen-Hao Shih

IPC分类号： H01L29/788

CPC分类号： H01L22/12 ,  H01L22/20 ,  H01L27/11531 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/0649

摘要： An integrated circuit device includes a substrate including a first region and a second region. A pit is formed in the first region. A stack of active layers alternating with insulating layers is deposited in the pit. The stack includes a particular insulating layer. The particular insulating layer has a first thickness, where a sum of the first thickness, thickness of active layers, and thicknesses of other insulating layers is essentially equal to a depth of the pit. The first thickness is different than the thicknesses of the other insulating layers by an amount within a range of process variations for the depth of the pit, for the thicknesses of the active layers, and for the thicknesses of other insulating layers. The device includes a planarized surface over the first and second regions, where an uppermost one of the active layers has a top surface below the planarized surface.

摘要翻译： 集成电路器件包括包括第一区域和第二区域的衬底。 在第一区域形成凹坑。 与绝缘层交替的一叠有源层沉积在凹坑中。 堆叠包括特定的绝缘层。 特定绝缘层具有第一厚度，其中第一厚度，有源层的厚度和其它绝缘层的厚度之和基本上等于凹坑的深度。 第一厚度不同于其它绝缘层的厚度，在凹坑的深度，有源层的厚度和其它绝缘层的厚度的工艺变化范围内的量。 该装置包括在第一和第二区域之上的平坦化表面，其中最上面的一个活性层在平坦化表面下方具有顶表面。

公开(公告)号：US20130175598A1

公开(公告)日：2013-07-11

申请号：US13347331

申请日：2012-01-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yen-Hao Shih

IPC分类号： H01L29/792 ,  H01L21/8239

CPC分类号： H01L27/11582 ,  H01L29/7926

摘要： The technology relates to a damascene word line for a three dimensional array of nonvolatile memory cells. Conductive lines such as silicon are formed over stacked nonvolatile memory structures. Word line trenches separate neighboring ones of the silicon lines. The silicon lines separated by the word line trenches are oxidized, making insulating surfaces in the word line trenches. Word lines are made in the word line trenches.

摘要翻译： 该技术涉及用于非易失性存储器单元的三维阵列的大马士革字线。 诸如硅的导电线形成在堆叠的非易失性存储器结构之上。 字线沟槽分离出相邻的硅线。 由字线沟槽分隔的硅线被氧化，在字线沟槽中形成绝缘表面。 字线是在字线沟中制作的。

公开(公告)号：US08426242B2

公开(公告)日：2013-04-23

申请号：US13076169

申请日：2011-03-30

申请人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

发明人： Huai-Yu Cheng ,  Chieh-Fang Chen ,  Hsiang-Lan Lung ,  Yen-Hao Shih ,  Simone Raoux ,  Matthew J. Breitwisch

IPC分类号： H01L21/06

CPC分类号： H01L47/00 ,  C23C14/06 ,  C23C14/0623 ,  C23C14/3414 ,  H01L21/06 ,  H01L27/24 ,  H01L45/144 ,  H01L45/1625

摘要： A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

摘要翻译： 使用包括硅或其它半导体的复合溅射靶和相变材料形成具有硅或另一半导体或硅基或其它基于半导体的添加剂的相变材料层。 硅或其他半导体的浓度比正在形成的层中规定浓度的硅或其它半导体的浓度高五倍以上。 对于GST型相变材料中的硅基添加剂，溅射靶可以包含超过40at％的硅。 可以在沉积期间使用复合溅射靶在溅射室中形成具有诸如氧或氮的反应气体流的硅基或其它基于半导体的添加剂。

公开(公告)号：US08406033B2

公开(公告)日：2013-03-26

申请号：US12488995

申请日：2009-06-22

申请人： Hsiang-Lan Lung ,  Yen-Hao Shih

发明人： Hsiang-Lan Lung ,  Yen-Hao Shih

IPC分类号： G11C11/00

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/3431 ,  G11C2013/0047 ,  G11C2013/0054 ,  G11C2013/0076

摘要： A programmable resistance memory device with a margin cell detection and refresh resources. Margin cell detection and refresh can include reading a selected cell, measuring a time interval which correlates with resistance of the selected cell during said reading, and enabling a refresh process if the measured time falls within a pre-specified range. The refresh process includes determining a data value stored in the selected cell, using for example a destructive read process, and refreshing the data value in the selected cell. The time interval can be measured by detecting timing within the sensing interval of a transition of voltage or current on a bit line across a threshold.

摘要翻译： 具有边缘单元检测和刷新资源的可编程电阻存储器件。 边缘细胞检测和刷新可以包括读取所选择的细胞，测量与所述读取期间所选细胞的电阻相关的时间间隔，以及如果测量的时间落在预定范围内，则启用刷新过程。 刷新过程包括使用例如破坏性读取处理确定存储在所选择的单元中的数据值，以及刷新所选择的单元中的数据值。 可以通过检测跨越阈值的位线上的电压或电流的转变的感测间隔内的定时来测量时间间隔。

公开(公告)号：US08363463B2

公开(公告)日：2013-01-29

申请号：US12729837

申请日：2010-03-23

申请人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

发明人： Yen-Hao Shih ,  Huai-Yu Cheng ,  Chieh-Fang Chen ,  Chao-I Wu ,  Ming Hsiu Lee ,  Hsiang-Lan Lung ,  Matthew J. Breitwisch ,  Simone Raoux ,  Chung H Lam

IPC分类号： G11C11/00

CPC分类号： H01L45/1625 ,  G11C13/0004 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1641

摘要： A phase change memory device with a memory element including a basis phase change material, such as a chalcogenide, and one or more additives, where the additive or additives have a non-constant concentration profile along an inter-electrode current path through a memory element. The use of “non-constant” concentration profiles for additives enables doping the different zones with different materials and concentrations, according to the different crystallographic, thermal and electrical conditions, and different phase transition conditions.

摘要翻译： 一种具有存储元件的相变存储器件，该存储元件包括诸如硫族化物的基本相变材料和一种或多种添加剂，其中所述添加剂或添加剂沿着穿过存储元件的电极间电流路径具有非恒定浓度分布 。 根据不同的晶体学，热学和电学条件以及不同的相变条件，使用非恒定浓度分布的添加剂可以使用不同的材料和浓度掺杂不同的区域。

公开(公告)号：US08324605B2

公开(公告)日：2012-12-04

申请号：US12286874

申请日：2008-10-02

申请人： Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

发明人： Hsiang-Lan Lung ,  Chieh-Fang Chen ,  Yen-Hao Shih ,  Ming-Hsiu Lee ,  Matthew J. Breitwisch ,  Chung Hon Lam ,  Frieder H. Baumann ,  Philip Flaitz ,  Simone Raoux

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/1226 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

摘要： A method for manufacturing a memory device, and a resulting device, is described using silicon oxide doped chalcogenide material. A first electrode having a contact surface; a body of phase change memory material in a polycrystalline state including a portion in contact with the contact surface of the first electrode, and a second electrode in contact with the body of phase change material are formed. The process includes melting and cooling the phase change memory material one or more times within an active region in the body of phase change material without disturbing the polycrystalline state outside the active region. A mesh of silicon oxide in the active region with at least one domain of chalcogenide material results. Also, the grain size of the phase change material in the polycrystalline state outside the active region is small, resulting in a more uniform structure.

摘要翻译： 使用氧化硅掺杂的硫族化物材料来描述用于制造存储器件的方法和所得到的器件。 具有接触表面的第一电极; 形成包括与第一电极的接触表面接触的部分的多晶状态的相变记忆材料体以及与相变材料体接触的第二电极。 该方法包括在相变材料体内的有源区内熔化和冷却相变存储材料一次或多次，而不会干扰有源区外的多晶态。 导致活性区域中的氧化硅网格与至少一个硫族化物材料结构域形成。 此外，活性区域外的多晶态的相变材料的晶粒尺寸小，结果更均匀。

公开(公告)号：US20110317480A1

公开(公告)日：2011-12-29

申请号：US12823508

申请日：2010-06-25

申请人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

发明人： HSIANG-LAN LUNG ,  Ming Hsiu Lee ,  Yen-Hao Shih ,  Tien-Yen Wang ,  Chao-I Wu

IPC分类号： G11C11/00 ,  H01L21/06

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0092

摘要： An integrated circuit phase change memory can be pre-coded by inducing a first resistance state in some cells and the memory, and a second resistance state and some other cells in the memory to represent a data set. The integrated circuit phase change memory is mounted on a substrate after coding the data set. After mounting the integrated circuit phase change memory, the data set is read by sensing the first and second resistance states, and changing cells in the first resistance state to a third resistance state and changing cells in the second resistance state to a fourth resistance state. The first and second resistance states maintain a sensing margin after solder bonding or other thermal cycling process. The third and fourth resistance states are characterized by the ability to cause a transition using higher speed and lower power, suitable for a mission function of a circuit.

摘要翻译： 集成电路相变存储器可以通过在一些单元和存储器中引起第一电阻状态以及存储器中的第二电阻状态以及存储器中的一些其他单元来表示数据集而被预编码。 在对数据集进行编码之后，将集成电路相变存储器安装在基板上。 在安装集成电路相变存储器之后，通过感测第一和第二电阻状态以及将第一电阻状态下的单元改变为第三电阻状态并将第二电阻状态的单元改变为第四电阻状态来读取数据组。 第一和第二电阻状态在焊接或其他热循环过程之后保持感测裕度。 第三和第四电阻状态的特征在于能够使用更高速度和更低功率的转换，适用于电路的任务功能。

公开(公告)号：US08084791B2

公开(公告)日：2011-12-27

申请号：US12619075

申请日：2009-11-16

申请人： Yen-Hao Shih

发明人： Yen-Hao Shih

IPC分类号： H01L27/148

CPC分类号： H01L29/66833 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： In a non-volatile memory structure, the source/drain regions are surrounded by a nitrogen-doped region. As a result, an interface between the substrate and the charge trapping layer above the nitrogen-doped region is passivated by a plurality of nitrogen atoms. The nitrogen atoms can improve data retention, and performance of cycled non-volatile memory devices.

摘要翻译： 在非易失性存储器结构中，源极/漏极区域被氮掺杂区域包围。 结果，在氮掺杂区上方的衬底和电荷俘获层之间的界面被多个氮原子钝化。 氮原子可以提高循环非易失性存储器件的数据保留性能和性能。