公开(公告)号：US09177870B2

公开(公告)日：2015-11-03

申请号：US13328382

申请日：2011-12-16

申请人： Hak-Lay Chuang ,  Ming Zhu

发明人： Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/02186 ,  H01L21/02192 ,  H01L21/3212 ,  H01L21/823842 ,  H01L21/823857

摘要： The present disclosure provides a method of fabricating a semiconductor device. A high-k dielectric layer is formed over a substrate. A first capping layer is formed over a portion of the high-k dielectric layer. A second capping layer is formed over the first capping layer and the high-k dielectric layer. A dummy gate electrode layer is formed over the second capping layer. The dummy gate electrode layer, the second capping layer, the first capping layer, and the high-k dielectric layer are patterned to form an NMOS gate and a PMOS gate. The NMOS gate includes the first capping layer, and the PMOS gate is free of the first capping layer. The dummy gate electrode layer of the PMOS gate is removed, thereby exposing the second capping layer of the PMOS gate. The second capping layer of the PMOS gate is transformed into a third capping layer.

摘要翻译： 本公开提供了制造半导体器件的方法。 在衬底上形成高k电介质层。 在高k电介质层的一部分上形成第一覆盖层。 在第一覆盖层和高k电介质层上形成第二覆盖层。 在第二盖层上形成虚拟栅电极层。 对虚拟栅极电极层，第二覆盖层，第一覆盖层和高k电介质层进行构图以形成NMOS栅极和PMOS栅极。 NMOS栅极包括第一覆盖层，PMOS栅极不含第一覆盖层。 去除PMOS栅极的伪栅极电极层，从而暴露PMOS栅极的第二覆盖层。 PMOS栅极的第二覆盖层被转换成第三覆盖层。

公开(公告)号：US20150296010A1

公开(公告)日：2015-10-15

申请号：US14249229

申请日：2014-04-09

申请人： Paul Xi ,  Ming Zhu ,  Xiaojun Feng ,  Mohamed Elzankaly ,  Marco Eidinger ,  Ananda Kumar Gajula ,  Mario Linge ,  Yang-cheng Fan ,  Oscar Marquez ,  Jianxun Zhou

发明人： Paul Xi ,  Ming Zhu ,  Xiaojun Feng ,  Mohamed Elzankaly ,  Marco Eidinger ,  Ananda Kumar Gajula ,  Mario Linge ,  Yang-cheng Fan ,  Oscar Marquez ,  Jianxun Zhou

IPC分类号： H04L29/08

CPC分类号： H04L67/1095 ,  H04L67/04 ,  H04L67/2861 ,  H04L67/32 ,  H04L69/24

摘要： A technique is described providing offline support to business applications. Offline support allows a business application running on a portable electronic device without connectivity to a backend server to operate as though the business application has access to a backend server. The technique receives a sync request for content from the portable electronic device. A sync task is generated from the sync requests and processed to generate a package that contains the desired content. Once the package is generated, the package is stored in a package repository and a download notification is transmitted to the portable electronic device to notify the user that the package is ready. The package can in turn be delivered to the portable electronic device when a download request is received from the portable electronic device.

摘要翻译： 描述了一种提供对业务应用程序的离线支持的技术。 离线支持允许在便携式电子设备上运行的业务应用程序，而无需连接到后端服务器，就像业务应用程序可以访问后端服务器一样进行操作。 该技术从便携式电子设备接收对内容的同步请求。 同步任务是从同步请求生成的，并被处理以生成包含所需内容的包。 一旦产生包装，该包就被存储在包储存库中，并且下载通知被传送到便携式电子设备以通知用户该包是否准备就绪。 当从便携式电子设备接收到下载请求时，该包可依次被传送到便携式电子设备。

公开(公告)号：US09142414B2

公开(公告)日：2015-09-22

申请号：US13331214

申请日：2011-12-20

申请人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

发明人： Sheng-Chen Chung ,  Ming Zhu ,  Harry-Hak-Lay Chuang ,  Bao-Ru Young ,  Wei-Cheng Wu ,  Chia Ming Liang ,  Sin-Hua Wu

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7848

摘要： A method includes forming a PMOS device. The method includes forming a gate dielectric layer over a semiconductor substrate and in a PMOS region, forming a first metal-containing layer over the gate dielectric layer and in the PMOS region, performing a treatment on the first metal-containing layer in the PMOS region using an oxygen-containing process gas, and forming a second metal-containing layer over the first metal-containing layer and in the PMOS region. The second metal-containing layer has a work function lower than a mid-gap work function of silicon. The first metal-containing layer and the second metal-containing layer form a gate of the PMOS device.

摘要翻译： 一种方法包括形成PMOS器件。 该方法包括在半导体衬底和PMOS区域上形成栅极电介质层，在栅极电介质层和PMOS区域上形成第一含金属层，对PMOS区域中的第一含金属层进行处理 使用含氧处理气体，并在第一含金属层和PMOS区域上形成第二含金属层。 第二含金属层具有低于硅的中间间隙功函数的功函数。 第一含金属层和第二含金属层形成PMOS器件的栅极。

公开(公告)号：US20150019156A1

公开(公告)日：2015-01-15

申请号：US14378954

申请日：2012-05-02

申请人： Maolin Pei ,  Ping Sun ,  Chunqiang Zhang ,  Jian Liu ,  Haimei Hu ,  Ming Zhu

发明人： Maolin Pei ,  Ping Sun ,  Chunqiang Zhang ,  Jian Liu ,  Haimei Hu ,  Ming Zhu

IPC分类号： G01R31/40 ,  G01R21/133

CPC分类号： G01R31/40 ,  G01R21/133 ,  H02J13/0079

摘要： A multi-node synchronous on-site test method, the method comprising: using GPS time as time reference, and conducting synchronous on-site tests on the devices to be tested and systems distributed at different places at an appointed time; controlling the synchronous phase control simulation devices distributed at multiple nodes via a synchronous test control center; within a uniform time section, synchronously outputting secondary side AC simulation signals, and simulating various actual operating conditions, thus achieving the detection of the monitoring and control performances of various dynamic monitoring and control systems, and ensuring the normal functions of the systems. The method of the present invention is able to conduct multi-node dynamic simulation test with synchronized GPS time, and achieves the detection of large-area multi-node monitoring and control systems. The present invention is suitable for the test of a wide area measurement system (WAMS) function, the simulation test of a damping control function, the simulation test of transiently stable state analysis and control functions, the simulation test of voltage stabilization and control functions, the simulation test of an islanding control function, the simulation test of wide area protection system functions and the like.

摘要翻译： 一种多节点同步现场测试方法，该方法包括：使用GPS时间作为时间参考，并对被测设备进行同步现场测试，并在指定时间内在不同地点分配系统; 通过同步测试控制中心控制分布在多个节点的同步相位控制仿真设备; 在均匀时间段内同步输出二次侧交流仿真信号，模拟各种实际运行状况，实现对各种动态监控系统的监控性能的检测，确保系统的正常功能。 本发明的方法能够进行同步GPS时间的多节点动态模拟测试，实现了大面积多节点监控系统的检测。 本发明适用于广域测量系统（WAMS）功能的测试，阻尼控制功能的仿真测试，瞬态稳态分析和控制功能的仿真测试，稳压控制功能的仿真测试， 孤岛控制功能的仿真测试，广域保护系统功能的仿真测试等。

公开(公告)号：US08889501B2

公开(公告)日：2014-11-18

申请号：US13486240

申请日：2012-06-01

申请人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

发明人： Harry-Hak-Lay Chuang ,  Sin-Hua Wu ,  Chung-Hau Fei ,  Ming Zhu ,  Bao-Ru Young ,  Yen-Ru Lee ,  Chii-Horng Li ,  Tze-Liang Lee

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L27/11

CPC分类号： H01L27/1116 ,  H01L21/823807 ,  H01L21/823814

摘要： A method includes forming a first gate stack of a first device over a semiconductor substrate, and forming a second gate stack of a second MOS device over the semiconductor substrate. A first epitaxy is performed to form a source/drain stressor for the second MOS device, wherein the source/drain stressor is adjacent to the second gate stack. A second epitaxy is performed to form a first silicon layer and a second silicon layer simultaneously, wherein the first silicon layer is over a first portion of the semiconductor substrate, and is adjacent the first gate stack. The second silicon layer overlaps the source/drain stressor.

摘要翻译： 一种方法包括在半导体衬底上形成第一器件的第一栅极堆叠，以及在半导体衬底上形成第二MOS器件的第二栅极堆叠。 执行第一外延以形成用于第二MOS器件的源/漏应力源，其中源极/漏极应力器与第二栅极堆叠相邻。 执行第二外延以同时形成第一硅层和第二硅层，其中第一硅层位于半导体衬底的第一部分之上并且与第一栅极堆叠相邻。 第二硅层与源极/漏极应力源重叠。

公开(公告)号：US08772114B2

公开(公告)日：2014-07-08

申请号：US13434969

申请日：2012-03-30

申请人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

发明人： Hak-Lay Chuang ,  Ming Zhu ,  Hui-Wen Lin ,  Bao-Ru Young

IPC分类号： H01L21/8234

CPC分类号： H01L29/4966 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

摘要： A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.

摘要翻译： 一种半导体制造方法，包括在所述基板的第一区域上形成第一功函数金属层，并在所述第一功函数金属层上和所述基板的第二区域上形成金属层。 在金属层上形成虚设层。 然后将这些层图案化以在第一区域中形成第一栅极结构，在衬底的第二区域中形成第二栅极结构。 然后去除虚拟层以暴露被处理的金属层。 处理可以是允许金属层用作第二功函数层的氧处理。

公开(公告)号：US08753931B2

公开(公告)日：2014-06-17

申请号：US13440848

申请日：2012-04-05

申请人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Ming Zhu ,  Jyun-Ming Lin ,  Wei Cheng Wu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L27/092

CPC分类号： H01L29/4941 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823443 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first gate structure and a second gate structure over a substrate. The first and second gate structures each include a high-k dielectric layer located over the substrate, a capping layer located over the high-k dielectric layer, an N-type work function metal layer located over the capping layer, and a polysilicon layer located over the N-type work function metal layer. The method includes forming an inter-layer dielectric (ILD) layer over the substrate, the first gate structure, and the second gate structure. The method includes polishing the ILD layer until a surface of the ILD layer is substantially co-planar with surfaces of the first gate structure and the second gate structure. The method includes replacing portions of the second gate structure with a metal gate. A silicidation process is then performed to the semiconductor device.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成第一栅极结构和第二栅极结构。 第一和第二栅极结构各自包括位于衬底上方的高k电介质层，位于高k电介质层上方的覆盖层，位于覆盖层上方的N型功函数金属层和位于 超过N型功函金属层。 该方法包括在衬底，第一栅极结构和第二栅极结构之上形成层间电介质（ILD）层。 该方法包括抛光ILD层，直到ILD层的表面与第一栅极结构和第二栅极结构的表面基本上共面。 该方法包括用金属栅极替换第二栅极结构的部分。 然后对半导体器件执行硅化处理。

公开(公告)号：US08703595B2

公开(公告)日：2014-04-22

申请号：US13299152

申请日：2011-11-17

申请人： Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

发明人： Hak-Lay Chuang ,  Cheng-Cheng Kuo ,  Ching-Che Tsai ,  Ming Zhu ,  Bao-Ru Young

IPC分类号： H01L21/336

CPC分类号： H01L27/0207 ,  H01L21/0274 ,  H01L21/28123 ,  H01L21/32139 ,  H01L21/823456 ,  H01L27/092 ,  H01L29/41775 ,  H01L29/42356 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates.

摘要翻译： 本公开提供了制造半导体器件的方法。 该方法包括在衬底上形成多个虚拟栅极。 虚拟门沿着第一轴延伸。 该方法包括在伪栅极上形成掩模层。 掩蔽层限定沿着不同于第一轴线的第二轴线延伸的细长开口。 开口暴露虚拟门的第一部分并保护虚拟门的第二部分。 开口的尖端部分的宽度大于开口的非尖端部分的宽度。 使用光学邻近校正（OPC）工艺形成掩模层。 该方法包括用多个第一金属栅极替换伪栅极的第一部分。 该方法包括用与第一金属栅极不同的多个第二金属栅极替换伪栅极的第二部分。

公开(公告)号：US08698252B2

公开(公告)日：2014-04-15

申请号：US13456939

申请日：2012-04-26

申请人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

发明人： Po-Nien Chen ,  Jin-Aun Ng ,  Ming Zhu ,  Bao-Ru Young ,  Hak-Lay Chuang

IPC分类号： H01L27/11

CPC分类号： H01L21/823842 ,  H01L21/28158 ,  H01L21/823857 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/0653 ,  H01L29/4933 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/78

摘要： A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a semiconductor substrate and isolation features to separate the different regions on the substrate. The different regions include a p-type field-effect transistor (pFET) core region, an input/output pFET (pFET IO) region, an n-type field-effect transistor (nFET) core region, an input/output nFET (nFET IO) region, and a high-resistor region.

摘要翻译： 描述了在基板的不同区域上具有五个栅极叠层的半导体器件及其制造方法。 该器件包括半导体衬底和用于分离衬底上的不同区域的隔离特征。 不同的区域包括p型场效应晶体管（pFET）芯区域，输入/输出pFET（pFET IO）区域，n型场效应晶体管（nFET）核心区域，输入/输出nFET（nFET） IO）区域和高电阻区域。

公开(公告)号：US20140061775A1

公开(公告)日：2014-03-06

申请号：US13599642

申请日：2012-08-30

申请人： Hak-Lay Chuang ,  Ming Zhu

发明人： Hak-Lay Chuang ,  Ming Zhu

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823828 ,  H01L21/823885 ,  H01L27/11273 ,  H01L29/42392

摘要： A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having a raised drain structure is also disclosed.

摘要翻译： 公开了一种形成具有升高的漏极结构的场效应晶体管的方法。 该方法包括：通过蚀刻半导体衬底来形成截头圆锥形源，所述截头圆锥形源突出在所述半导体衬底的平坦表面上方; 形成晶体管栅极，所述晶体管栅极的第一部分围绕所述截头圆锥形源的一部分，并且所述栅极的第二部分被配置为耦合到第一电触头; 以及形成具有凸起部分的漏极，所述凸起部分被配置为耦合到第二电接触并且位于与所述晶体管栅极的第二部分在所述半导体衬底的平面表面上方相同的高度处。 还公开了一种具有升高的漏极结构的半导体器件。