公开(公告)号：US06677194B2

公开(公告)日：2004-01-13

申请号：US10162573

申请日：2002-06-06

申请人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

发明人： Toshiaki Yamanaka ,  Akio Nishida ,  Yasuko Yoshida ,  Shuji Ikeda ,  Kenichi Kuroda ,  Shiro Kamohara ,  Shinichiro Kimura ,  Eiichi Murakami ,  Hideyuki Matsuoka ,  Masataka Minami

IPC分类号： H01L218238

CPC分类号： H01L21/823807 ,  H01L21/2652 ,  H01L21/823842 ,  H01L21/823892

摘要： A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.

摘要翻译： 低阈值电压NMIS区域和高阈值电压PMIS区域由也用于阱形成的光致抗蚀剂掩模设置。 使用具有用于NMIS和PMIS的开口的光致抗蚀剂掩模，通过一个离子注入步骤设置NMIS和PMIS区域。 栅极氧化后，离子注入通过非晶硅膜导入孔，通道和栅电极。 可以设置多个CMIS阈值电压，并且可以以减少数量的步骤使用光致抗蚀剂形成两个极性的栅电极。 这解决了需要光掩模的问题，因为存在孔，通道阻挡件，栅电极和阈值电压控制的离子注入类型，因此制造步骤的数量和生产成本增加。

公开(公告)号：US06576512B2

公开(公告)日：2003-06-10

申请号：US10251850

申请日：2002-09-23

申请人： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

发明人： Yasuhiro Taniguchi ,  Shoji Shukuri ,  Kenichi Kuroda ,  Shuji Ikeda ,  Takashi Hashimoto

IPC分类号： H01L21336

CPC分类号： H01L27/0922 ,  H01L21/26513 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/11546 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7835 ,  Y10S438/981

摘要： A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

摘要翻译： 能够进行高速运转的MISFET包括在自对准的基础上与栅极侧壁层对准的高浓度区域的金属硅化物层。 可以以高电压驱动的MISFET包括具有大于侧壁层的宽度的宽度的LDD部分，与LDD部分接触的高浓度区域和高浓度区域中的金属硅化物层。

公开(公告)号：US06576509B1

公开(公告)日：2003-06-10

申请号：US09639305

申请日：2000-08-16

申请人： Shigeya Toyokawa ,  Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Yoshida ,  Toshiyuki Iwaki ,  Masamichi Matsuoka

发明人： Shigeya Toyokawa ,  Takashi Hashimoto ,  Kenichi Kuroda ,  Shoji Yoshida ,  Toshiyuki Iwaki ,  Masamichi Matsuoka

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L21/76877 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91

摘要： In forming a plug 21 of a polycrystalline silicon film in a contact hole 19 to which a bit line BL is connected, the upper surface of the plug 21 is retracted downward from the upper edge of the contact hole 19, and a plug 22 of a laminate of a TiN film 26 and a W film 27 is formed on the plug 21. Then, the W film deposited on the contact hole 19 is patterned to form a bit line BL having a width narrower than the diameter of the contact hole 19. Here, the W film 27 constituting part of the plug 22 in the contact hole 19 is etched, but the TiN film 26 constituting another part of the plug 22 is not almost etched.

摘要翻译： 在连接有位线BL的接触孔19中形成多晶硅膜的插头21时，插头21的上表面从接触孔19的上边缘向下缩回，并且插头22 在插塞21上形成TiN膜26和W膜27的层压体。然后，将沉积在接触孔19上的W膜图案化，形成宽度比接触孔19的直径窄的位线BL。 这里，构成接触孔19中的插头22的一部分的W膜27被蚀刻，但构成插头22的另一部分的TiN膜26几乎不被蚀刻。

公开(公告)号：US06335879B1

公开(公告)日：2002-01-01

申请号：US09705835

申请日：2000-11-06

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1400

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有和电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储单元的可重写非易失性存储器，并且被设置为便于闪速擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US06181598B2

公开(公告)日：2001-01-30

申请号：US09435037

申请日：1999-11-05

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G06F9/445 ,  G06F15/7814 ,  G06F15/7821 ,  G11C7/1045 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  Y02D10/43

摘要： A semiconductor device having and electrically erasable and programmable nonvolatile memory, for example, a rewritable nonvolatile memory including memory cells arranged in rows and columns and disposed to facilitate both flash erasure as well as selective erasure of individual units of plural memory cells. The semiconductor device which functions as a microcomputer chip also has a processing unit and includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of a processing unit and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 具有和电可擦除和可编程非易失性存储器的半导体器件，例如，包括以行和列布置的存储单元的可重写非易失性存储器，并且被设置为便于闪速擦除以及多个存储器单元的各个单元的选择性擦除。 用作微计算机芯片的半导体器件还具有处理单元，并且包括：输入端子，用于在处理单元的控制下在闪速存储器被重写的第一操作模式和第二操作模式之间接收用于切换微型计算机的操作模式信号 操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US5610420A

公开(公告)日：1997-03-11

申请号：US427253

申请日：1995-04-24

申请人： Kenichi Kuroda ,  Masaaki Terasawa ,  Kiyoshi Matsubara

发明人： Kenichi Kuroda ,  Masaaki Terasawa ,  Kiyoshi Matsubara

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L27/11546

摘要： A plurality of memory cells have their sources and drains formed integrally with n.sup.+ -buried layers acting as first data lines in a semiconductor substrate. The n.sup.+ -buried layers are connected with second data lines through transfer MISFETs. These transfer MISFETs have their gates made of the same layer of polycrystalline silicon as that of the floating gates of memory cells are shunted at each predetermined number of bits by Al lines having a lower resistance than that of the polycrystalline silicon.

摘要翻译： 多个存储单元的源极和漏极与在半导体衬底中用作第一数据线的n +层作为一体形成。 n +掩埋层通过传输MISFET与第二数据线连接。 这些转移MISFET的栅极由具有比多晶硅电阻低的Al线在每个预定位数被分流的同一多晶硅层制成。

公开(公告)号：US5581503A

公开(公告)日：1996-12-03

申请号：US520721

申请日：1995-07-31

申请人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

发明人： Kiyoshi Matsubara ,  Naoki Yashiki ,  Shiro Baba ,  Takashi Ito ,  Hirofumi Mukai ,  Masanao Sato ,  Masaaki Terasawa ,  Kenichi Kuroda ,  Kazuyoshi Shiba

IPC分类号： G06F9/445 ,  G06F15/78 ,  G11C7/10 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11526 ,  G06F15/7814 ,  G06F15/7821 ,  G06F9/445 ,  G11C16/0416 ,  G11C16/102 ,  G11C16/105 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3445 ,  G11C16/3459 ,  G11C7/1045 ,  H01L27/115 ,  H01L27/11531 ,  H01L27/11546 ,  H01L27/105 ,  Y02B60/185

摘要： An electrically rewritable flash memory device which has a memory cell array arranged in rows and columns of memory cells and which is divided into a plurality of memory blocks having different memory capacities. Each memory block having one or more rows of memory cells. A common voltage control circuit is provided for each of the memory blocks for applying a first potential to a common conductor for a memory block containing a memory cell selected with a selection voltage applied to its associated data line conductor for a writing operation and a second potential higher than the first potential to a common conductor for a memory block containing a memory cell unselected with the selection voltage applied to its associated data line conductor and containing no selected memory cell for a writing operation. A microcomputer having a CPU and the above-mentioned electrically rewritable flash memory formed in a single semiconductor chip includes an input terminal for receiving an operation mode signal for switching the microcomputer between a first operation mode in which the flash memory is rewritten under control of the CPU and a second operation mode in which the flash memory is rewritten under control of separate writing circuit externally connectable to the microcomputer.

摘要翻译： 一种电可重写闪速存储器件，其具有以存储单元的行和列布置的存储单元阵列，并且被分成具有不同存储容量的多个存储块。 每个存储器块具有一行或多行存储器单元。 为每个存储块提供公共电压控制电路，用于将第一电位施加到用于存储块的公共导体，该存储块包含用施加到其相关联的数据线导体的写入操作和第二电位的选择电压选择的存储器单元 高于用于存储块的公共导体的第一电位，该存储块包含未选择施加到其相关联的数据线导体的选择电压并且不包含用于写入操作的选定存储器单元的存储器单元。 具有CPU和上述形成在单个半导体芯片中的电可重写闪存的微型计算机包括：输入端子，用于接收用于在微控制器的控制下在闪速存储器被重写的第一操作模式之间切换微型计算机的操作模式信号 CPU和第二操作模式，其中在外部连接到微型计算机的分离的写入电路的控制下闪存被重写。

公开(公告)号：US5445987A

公开(公告)日：1995-08-29

申请号：US98779

申请日：1993-07-29

申请人： Kenichi Kuroda ,  Masaaki Terasawa ,  Kiyoshi Matsubara

发明人： Kenichi Kuroda ,  Masaaki Terasawa ,  Kiyoshi Matsubara

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/266

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11536 ,  H01L27/11546

摘要： A plurality of memory cells have their sources and drains formed integrally with n.sup.+ -buried layers acting as first data lines in a semiconductor substrate. The n.sup.+ -buried layers are connected with second data lines through transfer MISFETs. These transfer MISFETs have their gates made of the same layer of polycrystalline silicon as that of the floating gates of memory cells and are shunted at each predetermined number of bits by Al lines having a lower resistance than that of the polycrystalline silicon. The aforementioned memory cells are made by a method comprising the steps of: forming over a semiconductor substrate sequentially the first gate insulating film, a first conductor layer for the floating gate electrode, an insulating film having at least its uppermost layer of a silicon nitride film for the second gate insulating film, and a damage preventing film of a silicon oxide film; patterning the silicon oxide film, the insulating film and the first conductor layer in a stripe shape; and forming, by ion implantation, an n.sup.+ -buried layer extending in a first direction by using the stripe-patterned silicon oxide film as a mask. As a result, the second gate insulating film can be prevented from having its quality degraded by the damage of the ion implantation.

摘要翻译： 多个存储单元的源极和漏极与在半导体衬底中用作第一数据线的n +层作为一体形成。 n +掩埋层通过传输MISFET与第二数据线连接。 这些转移MISFET具有与存储单元的浮动栅极相同的多晶硅层制成的栅极，并且通过具有比多晶硅的电阻低的Al线以每个预定数量的位分流。 上述存储单元通过以下方法制造：包括以下步骤：依次形成半导体衬底上的第一栅绝缘膜，用于浮置栅电极的第一导体层，至少具有氮化硅膜的最上层的绝缘膜 用于第二栅极绝缘膜，以及氧化硅膜的防损伤膜; 将氧化硅膜，绝缘膜和第一导体层图案化为条状; 以及通过使用条状图案化的氧化硅膜作为掩模，通过离子注入形成沿第一方向延伸的n +掩埋层。 结果，可以防止第二栅极绝缘膜由于离子注入的损坏而劣化其质量。

公开(公告)号：US5270944A

公开(公告)日：1993-12-14

申请号：US929511

申请日：1992-08-14

申请人： Kenichi Kuroda ,  Akinori Matsuo

发明人： Kenichi Kuroda ,  Akinori Matsuo

IPC分类号： H01L21/8246 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/105 ,  H01L27/112 ,  G06F15/60 ,  H01L27/00

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11286 ,  H01L27/11546 ,  H01L27/0207

摘要： A method of fabrication comprising forming a semiconductor integrated circuit device LSI which has a microcomputer CPU furnished with an EPROM, determining a program for controlling the microcomputer CPU and to be set in the EPROM (performing an initial evaluation) while information is being written into and erased from the EPROM built in the semiconductor integrated circuit device LSI, and thereafter forming a semiconductor integrated circuit device LSI in which the EPROM of the first-mentioned semiconductor integrated circuit device LSI is replaced with a mask ROM. In replacing the EPROM with the mask ROM, peripheral circuits required for both the EPROM and the mask ROM have their circuit arrangements held basically the same, and specific peripheral circuits for use in only the EPROM have their circuit regions left as they are as logically inactive regions.

摘要翻译： 一种制造方法，包括形成半导体集成电路器件LSI，其具有配备有EPROM的微型计算机CPU，确定用于控制微机CPU的程序并将其设置在EPROM中（执行初始评估），同时正在写入信息;以及 从内置于半导体集成电路器件LSI中的EPROM擦除，然后形成半导体集成电路器件LSI，其中首先提到的半导体集成电路器件LSI的EPROM被掩模ROM替代。 在使用掩模ROM替换EPROM时，EPROM和掩模ROM所需的外围电路的电路布置基本相同，仅在EPROM中使用的特定外围电路的电路区域保持不变，因为它们在逻辑上不起作用 地区。

公开(公告)号：US09493319B2

公开(公告)日：2016-11-15

申请号：US14255015

申请日：2014-04-17

申请人： Fumiaki Tsuchiya ,  Kenichi Kuroda ,  Yasuhiro Tomita ,  Maki Nishide

发明人： Fumiaki Tsuchiya ,  Kenichi Kuroda ,  Yasuhiro Tomita ,  Maki Nishide

IPC分类号： G03G15/00 ,  B65H5/26 ,  B65H7/20

CPC分类号： B65H5/26 ,  B65H7/20 ,  B65H2301/5111 ,  B65H2511/512 ,  G03G15/602

摘要： An automatic document feeder includes a sheet feeding tray on which a document is stacked; a slit glass on which the document is scanned while moving; a discharge path in which the document is conveyed after the document is scanned; a document discharge unit to which the document is discharged through the discharge path; and a stamp device that makes a mark on a scanned surface of the document being in the discharge path. The stamp device includes a printing unit that faces the scanned surface of the document. The printing unit is movable between a first position at which the printing unit faces the document being in the discharge path and a second position at which the printing unit is retracted from the discharge path.

摘要翻译： 自动送纸器包括一个纸张馈送托盘，文档被堆叠在其上; 移动时扫描文件的狭缝玻璃; 在文件被扫描之后文档被传送的排放路径; 原稿排出单元，通过排出路径将文件排出到该文件排出单元; 以及在文档的扫描表面上形成标记的印模装置处于排出路径。 邮票装置包括面向文件扫描表面的打印单元。 打印单元可以在打印单元面对在排出路径中的文档的第一位置和打印单元从排出路径缩回的第二位置之间移动。