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81.发明授权Manufacturing a semiconductor package including an embedded circuit component within a support structure of the package 有权制造包括在封装的支撑结构内的嵌入式电路部件的半导体封装公开(公告)号：US09129908B2
公开(公告)日：2015-09-08
申请号：US13296707
申请日：2011-11-15
Applicant: Jovica Savic , Zhiping Yang , Jie Xue , Li Li
Inventor： Jovica Savic , Zhiping Yang , Jie Xue , Li Li
CPC classification number: H05K1/183 , H01L23/24 , H01L23/3107 , H01L23/49838 , H01L2224/16225 , H01L2924/0002 , H05K1/115 , H05K1/181 , H05K2201/095 , H05K2201/10492 , H05K2201/10507 , H01L2924/00
Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.
Abstract translation: 提供了一种方法和装置，其中空腔形成在支撑结构中，支撑结构可操作以支撑半导体器件，将电路元件的至少一部分设置在支撑结构中的空腔中，将空腔填充在 支撑结构，其具有不导电的填充材料，以至少部分地围绕电路元件与非导电填充材料，并将半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。
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公开(公告)号：US08908384B2
公开(公告)日：2014-12-09
申请号：US13491378
申请日：2012-06-07
Applicant: Morgan Johnson , Frederick G. Weiss
Inventor： Morgan Johnson , Frederick G. Weiss
CPC classification number: G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
Abstract: A computing device has a motherboard circuit substrate having at least one layer of electrical interconnects and a socket arranged to receive a main processor for the computing device, the socket electrically coupled to at least a portion of the layer of electrical interconnects, wherein the circuit substrate has no memory interconnects.
Abstract translation: 计算设备具有具有至少一层电互连层的母板电路基板和布置成接收用于计算设备的主处理器的插座，该插座电耦合到电互连层的至少一部分，其中电路基板 没有内存互连。
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公开(公告)号：US08363418B2
公开(公告)日：2013-01-29
申请号：US13163502
申请日：2011-06-17
Applicant: Morgan Johnson , Frederick G. Weiss
Inventor： Morgan Johnson , Frederick G. Weiss
IPC: H05K7/00
CPC classification number: G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.
Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。
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公开(公告)号：US20120262875A1
公开(公告)日：2012-10-18
申请号：US13163502
申请日：2011-06-17
Applicant: Morgan Johnson , Frederick G. Weiss
Inventor： Morgan Johnson , Frederick G. Weiss
CPC classification number: G06F13/16 , G06F1/32 , G06F13/4068 , G11C5/04 , H01L23/32 , H01L23/49838 , H01L23/4985 , H01L2924/0002 , H05K1/0237 , H05K1/0243 , H05K1/0296 , H05K1/111 , H05K1/115 , H05K1/141 , H05K1/147 , H05K1/181 , H05K1/189 , H05K2201/095 , H05K2201/10159 , H05K2201/10189 , H05K2201/10378 , H05K2201/10515 , H05K2201/10522 , Y02D10/151 , Y10T29/4913 , H01L2924/00
Abstract: An interposer substrate includes an array of interconnects in the interposer substrate, the array of connectors arranged in accordance with an array of interconnects for a processor on a circuit substrate, at least one conductive trace in the interposer substrate in connection with at least one connector in the array of interconnects, the conductive trace arranged parallel to the interposer substrate such that no electrical connection exists between the connector in the interposer substrate and a corresponding one of the interconnects for the processor on the circuit substrate, and at least one peripheral circuit residing on the interposer substrate in electrical connection with the conductive trace.
Abstract translation: 插入器衬底包括插入器衬底中的互连阵列，所述连接器阵列根据用于电路衬底上的处理器的互连阵列布置，所述插入器衬底中的至少一个导电迹线与至少一个连接器 所述互连阵列，所述导电迹线平行于所述插入器基板布置，使得在所述插入器基板中的所述连接器与所述电路基板上的所述处理器的相应的一个互连件之间不存在电连接;以及至少一个外围电路， 所述插入器衬底与所述导电迹线电连接。
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