中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.02 seconds)

    MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE
    1.
    发明申请
    MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE 有权
    在包装的支持结构中制造包括嵌入式电路组件的半导体封装

    公开(公告)号：US20130122658A1

    公开(公告)日：2013-05-16

    申请号：US13296707

    申请日：2011-11-15

    Applicant: Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

    Inventor： Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

    IPC: H01L21/56

    CPC classification number: H05K1/183 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/095 ,  H05K2201/10492 ,  H05K2201/10507 ,  H01L2924/00

    Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

    Abstract translation: 提供了一种方法和装置，其中空腔形成在支撑结构中，支撑结构可操作以支撑半导体器件，将电路元件的至少一部分设置在支撑结构中的空腔中，将空腔填充在 支撑结构，其具有不导电的填充材料，以至少部分地围绕电路元件与非导电填充材料，并将半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。

    Techniques for alleviating the need for DC blocking capacitors in high-speed differential signal pairs
    2.
    发明授权
    Techniques for alleviating the need for DC blocking capacitors in high-speed differential signal pairs 有权
    用于缓解高速差分信号对中对直流阻塞电容器的需求的技术

    公开(公告)号：US07262974B2

    公开(公告)日：2007-08-28

    申请号：US11261014

    申请日：2005-10-28

    Applicant: Zhiping Yang ,  Vinayagam Arumugham

    Inventor： Zhiping Yang ,  Vinayagam Arumugham

    IPC: H05K7/00

    CPC classification number: H05K1/0245 ,  H01L2223/6638 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09236 ,  H05K2201/09309 ,  H05K2201/10689

    Abstract: A circuit board has a first component interface configured to connect to a first circuit board component, a second component interface configured to connect to a second circuit board component, a differential signal pair electrically connecting the first component interface to the second component interface, and a signal return path configured to operate as a signal return pathway for the differential signal pair. The signal return path includes first conductive material which is in electrical communication with the first component interface, second conductive material which is in electrical communication with the second component interface, and a dielectric which provides direct current separation between the first and second conductive material. Such a circuit board may alleviate the need for DC blocking capacitors along the differential pair, and along other differential pairs when the circuit board has multiple differential pairs connecting the first and second component interfaces.

    Abstract translation: 电路板具有被配置为连接到第一电路板部件的第一部件接口，被配置为连接到第二电路板部件的第二部件接口，将第一部件接口电连接到第二部件接口的差分信号对，以及 信号返回路径被配置为用作差分信号对的信号返回路径。 信号返回路径包括与第一部件接口电连通的第一导电材料，与第二部件接口电连通的第二导电材料以及在第一和第二导电材料之间提供直流电隔离的电介质。 当电路板具有连接第一和第二组件接口的多个差分对时，这样的电路板可以减轻沿着差分对的隔离电容器的需要，以及沿着其它差分对的需要。

    Optical Module Design in an SFP Form Factor to Support Increased Rates of Data Transmission
    4.
    发明申请
    Optical Module Design in an SFP Form Factor to Support Increased Rates of Data Transmission 有权
    SFP格式的光模块设计，以支持数据传输速率的提高

    公开(公告)号：US20120230700A1

    公开(公告)日：2012-09-13

    申请号：US13045972

    申请日：2011-03-11

    Applicant: Luca Cafiero ,  Zhiping Yang ,  Victor Odisho ,  Francisco Matus

    Inventor： Luca Cafiero ,  Zhiping Yang ,  Victor Odisho ,  Francisco Matus

    IPC: H04B10/00

    CPC classification number: G02B6/4201 ,  H05K1/117 ,  H05K2201/09409 ,  H05K2201/10121

    Abstract: A small form-factor pluggable (SFP) module includes a board with an end portion to be inserted into a connector device. A first set of signal pads is arranged along an edge of a first surface of the SFP board at the end portion and a second set of signal pads along an edge of a second surface of the SFP board at the end portion. A third set of signal pads is disposed on the second surface at the end portion, offset from the edge of the second surface. A transceiver, coupled to the signal pads of the first, second, and third sets of signal pads, is configured to transmit and receive signals via the third set of signal pads and to transmit and receive signals via at least one of the first and second sets of signal pads.

    Abstract translation: 小尺寸可插拔（SFP）模块包括具有插入连接器装置的端部的板。 第一组信号焊盘沿端部的SFP板的第一表面的边缘和沿端部的SFP板的第二表面的边缘的第二组信号焊盘排列。 第三组信号垫设置在端部处的第二表面上，偏离第二表面的边缘。 耦合到第一，第二和第三组信号焊盘的信号焊盘的收发器被配置成经由第三组信号焊盘发送和接收信号，并且经由第一和第二信号焊盘中的至少一个来发送和接收信号 套信号垫。

    Computer-Implemented Systems And Methods For Dynamic Model Switching Simulation Of Risk Factors
    7.
    发明申请
    Computer-Implemented Systems And Methods For Dynamic Model Switching Simulation Of Risk Factors 审中-公开
    计算机实现的系统和方法用于动态模型切换模拟风险因素

    公开(公告)号：US20110153536A1

    公开(公告)日：2011-06-23

    申请号：US12640881

    申请日：2009-12-17

    Applicant: Zhiping Yang ,  Donald James Erdman ,  Wei Chen

    Inventor： Zhiping Yang ,  Donald James Erdman ,  Wei Chen

    IPC: G06N5/02 ,  G06F17/10

    CPC classification number: G06F17/18 ,  G06F17/5009 ,  G06F2217/10 ,  G06Q40/08

    Abstract: Computer-implemented systems and methods are provided for implementing a dynamic model switching simulator that generates a plurality of simulations. A system and method generates a simulation comprising predictions over a plurality of time periods. Generating a simulation includes generating a first time period prediction using a first model of a first model type. Generating the plurality of subsequent time period predictions includes evaluating the model switching rule to identify whether to switch models for a subsequent time period prediction, generating the subsequent time period prediction using the first model if a switch of models is not identified, and generating the subsequent time period prediction using a second model of a second model type otherwise.

    Abstract translation: 提供了计算机实现的系统和方法来实现产生多个模拟的动态模型切换模拟器。 系统和方法产生包括多个时间周期的预测的模拟。 生成模拟包括使用第一模型类型的第一模型生成第一时间段预测。 产生多个随后的时间段预测包括评估模型切换规则以识别是否为随后的时间段预测切换模型，如果模型的切换未被识别，则使用第一模型生成随后的时间段预测，并且生成后续的 否则使用第二模型类型的第二模型进行时段预测。

    Methods and apparatus for providing a power signal to an area array package
    8.
    发明授权
    Methods and apparatus for providing a power signal to an area array package 有权
    用于向区域阵列封装提供功率信号的方法和装置

    公开(公告)号：US07675147B1

    公开(公告)日：2010-03-09

    申请号：US11936577

    申请日：2007-11-07

    Applicant: Kenneth Hubbard ,  Jie Xue ,  Yida Zou ,  Zhiping Yang

    Inventor： Kenneth Hubbard ,  Jie Xue ,  Yida Zou ,  Zhiping Yang

    IPC: H01L23/495

    CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0263 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/613

    Abstract: An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

    Abstract translation: 区域阵列器件具有耦合到器件的耦合表面并被配置为在区域阵列封装和电路板之间传送数据信号的主要电触点的栅格阵列。 区域阵列器件还具有耦合到器件的耦合表面的另外的一系列辅助电触点，并被配置为在区域阵列封装和电路板之间承载功率信号。 附加的一系列次级电触点为区域阵列封装提供相对大量的电力，同时允许制造商保持配置为承载数据信号的电网阵列的初级电触点的数量，并因此保持区域阵列的整体性能 包。

    Techniques for manufacturing a circuit board with an improved layout for decoupling capacitors
    9.
    发明授权
    Techniques for manufacturing a circuit board with an improved layout for decoupling capacitors 有权
    用于制造电路板的技术，其具有用于去耦电容器的改进的布局

    公开(公告)号：US07360307B2

    公开(公告)日：2008-04-22

    申请号：US11283446

    申请日：2005-11-18

    Applicant: Zhiping Yang ,  Vinayagam Arumugham ,  Lekhanh Dang

    Inventor： Zhiping Yang ,  Vinayagam Arumugham ,  Lekhanh Dang

    IPC: H05K3/34 ,  H01K3/10

    CPC classification number: H05K1/0231 ,  H05K1/114 ,  H05K2201/09418 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165

    Abstract: A circuit board module has an IC device, discrete components, and a circuit board structure in electrical communication with the IC device and the discrete component. The circuit board structure includes non-conductive material defining a top surface of the circuit board structure and a bottom surface of the circuit board structure, vias supported by the non-conductive material, top pads electrically coupled to the vias, and bottom pads electrically coupled to the vias. The top pads are disposed along the top surface of the circuit board structure and are soldered to IC device. The bottom pads are disposed along the bottom surface of the circuit board structure and are configured to solder to the discrete components. The bottom pads include a group of angled bottom pads which is soldered to a group of the discrete components substantially at 45 degree angles relative to sides of the IC device.

    Abstract translation: 电路板模块具有与IC器件和分立部件电连通的IC器件，分立部件和电路板结构。 电路板结构包括限定电路板结构的顶表面和电路板结构的底表面的非导电材料，由非导电材料支撑的通孔，电耦合到通孔的顶部焊盘和电耦合的底部焊盘 到通道 顶焊盘沿着电路板结构的顶表面设置，并被焊接到IC器件。 底部焊盘沿着电路板结构的底表面设置并且被配置为焊接到分立部件。 底部焊盘包括一组倾斜的底部焊盘，其相对于IC器件的侧面基本上以45度角焊接到一组分立部件。

    Methods and apparatus for providing a power signal to an area array package
    10.
    发明授权
    Methods and apparatus for providing a power signal to an area array package 有权
    用于向区域阵列封装提供功率信号的方法和装置

    公开(公告)号：US07303941B1

    公开(公告)日：2007-12-04

    申请号：US10799479

    申请日：2004-03-12

    Applicant: Kenneth Hubbard ,  Jie Xue ,  Yida Zou ,  Zhiping Yang

    Inventor： Kenneth Hubbard ,  Jie Xue ,  Yida Zou ,  Zhiping Yang

    IPC: H01L21/44

    CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K1/0263 ,  H05K3/3436 ,  H05K2201/094 ,  H05K2201/10734 ,  Y02P70/613

    Abstract: An area array device has a grid array of primary electrical contacts coupled to a coupling surface of the device and configured to carry data signals between the area array package and a circuit board. The area array device also has an additional series of secondary electrical contacts coupled to the coupling surface of the device and configured to carry power signals between the area array package and the circuit board. The additional series of secondary electrical contacts provides a relatively large amount of power to the area array package while allowing a manufacturer to maintain the number of primary electrical contacts of the grid array configured to carrying data signals and therefore maintain the overall performance of the area array package.

    Abstract translation: 区域阵列器件具有耦合到器件的耦合表面并被配置为在区域阵列封装和电路板之间传送数据信号的主要电触点的栅格阵列。 区域阵列器件还具有耦合到器件的耦合表面的另外的一系列辅助电触点，并被配置为在区域阵列封装和电路板之间承载功率信号。 附加的一系列次级电触点为区域阵列封装提供相对大量的电力，同时允许制造商保持配置为承载数据信号的电网阵列的初级电触点的数量，并因此保持区域阵列的整体性能 包。

Patent Agency Ranking