公开(公告)号：US11036662B2

公开(公告)日：2021-06-15

申请号：US16806759

申请日：2020-03-02

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kyohei Yamaguchi ,  Daisuke Kawakami ,  Hiroyuki Hamasaki

IPC: G06F13/24 ,  G06F11/07

Abstract: A semiconductor device includes an interrupt control circuit that receives a plurality of interrupt signals from the circuit blocks and outputs an interrupt request to the processor, and an interrupt monitoring circuit that corresponds to one of the interrupt signals and includes a setting circuit for setting a monitoring type and first and second monitoring periods. If the monitoring type indicates an asserted state of the interrupt signal, the interrupt monitoring circuit monitors the asserted state. If a first duration of the continuous asserted state exceeds the first monitoring period, the interrupt monitoring circuit detects the state as a failure. If the monitoring type indicates a negated state of the interrupt signal, the interrupt monitoring circuit monitors the negated state. If a second duration of the continuous negated state exceeds the second monitoring period, the interrupt monitoring circuit detects the state as a failure.

公开(公告)号：US11030142B2

公开(公告)日：2021-06-08

申请号：US15635299

申请日：2017-06-28

Applicant: Intel Corporation

Inventor： Kenneth P. Foust ,  Amit Kumar Srivastava ,  Nobuyuki Suzuki

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/364 ,  G06F13/24

Abstract: In an embodiment, a host controller includes a clock control circuit to cause the host controller to communicate a clock signal on a clock line of an interconnect, the clock control circuit to receive an indication that a first device is to send information to the host controller and to dynamically release control of the clock line of the interconnect to enable the first device to drive a second clock signal onto the clock line of the interconnect for communication with the information. Other embodiments are described and claimed.

公开(公告)号：US20210133022A1

公开(公告)日：2021-05-06

申请号：US17147555

申请日：2021-01-13

Applicant: Dell Products L.P.

Inventor： Ching-Lung Chao ,  Shih-Hao Wang ,  Zhengyu Yang

IPC: G06F11/10 ,  G06F11/07 ,  G11C29/52 ,  G06F9/4401 ,  G06F13/24

Abstract: A memory scrubbing system includes a persistent memory device coupled to an operating system (OS) and a Basic Input/Output System (BIOS). During a boot process and prior to loading the OS, the BIOS retrieves a known memory location list that identifies known memory locations of uncorrectable errors in the persistent memory device and performs a partial memory scrubbing operation on the known memory locations. The BIOS adds any known memory locations that maintain an uncorrectable error to a memory scrub error list. The BIOS then initiates a full memory scrubbing operation on the persistent memory device, cause the OS to load and enter a runtime environment while the full memory scrubbing operation is being performed, and provides the memory scrub error list to the OS.

公开(公告)号：US10990544B2

公开(公告)日：2021-04-27

申请号：US16421719

申请日：2019-05-24

Applicant: NXP USA, Inc.

Inventor： Tiefei Zang ,  Mingkai Hu ,  Gang Liu ,  Minghuan Lian

IPC: G06F13/24 ,  G06F13/28 ,  G06F13/42

Abstract: A method and apparatus for generating a message interrupt. In one embodiment, the method includes writing a predefined data pattern to a predetermined source location in a memory system. One or more first data blocks are also stored in the memory system at one or more first locations, respectively. After storing the one or more first data blocks at the one or more first source locations, creating a first data structure that comprises one or more first source addresses mapped to one or more first destination addresses, respectively, and a predetermined source address mapped to a predetermined destination address, wherein the one or more first source addresses correspond to the one or more first source locations, respectively, and wherein the predetermined source address corresponds to a predetermined source location. The first data structure can be used by a DMA controller to transfer data stored at the one or more first storage locations and to transfer the predetermined data.

公开(公告)号：US10990407B2

公开(公告)日：2021-04-27

申请号：US13977605

申请日：2012-04-24

Applicant: Peter P. Waskiewicz, Jr.

Inventor： Peter P. Waskiewicz, Jr.

IPC: G06F9/38 ,  G06F13/24 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/48

Abstract: Methods, apparatus, and systems for facilitating effective power management through dynamic reconfiguration of interrupts. Interrupt vectors are mapped to various processor cores in a multi-core processor, and interrupt workloads on the processor cores are monitored. When an interrupt workload for a given processor core is detected to fall below a threshold, the interrupt vectors are dynamically reconfigured by remapping interrupt vectors that are currently mapped to the processor core to at least one other processor core, such that there are no interrupt vectors mapped to the processor core after reconfiguration. The core is then enabled to be put in a deeper idle state. Similar operations can be applied to additional processor cores, effecting a collapsing of interrupt vectors onto fewer processor cores. In response to detecting cores emerging from idle states, reconfiguration of interrupt vectors can be performed to rebalance the assignment of the vectors across active cores by remapping a portion of the vectors to those cores.

公开(公告)号：US20210117351A1

公开(公告)日：2021-04-22

申请号：US17063745

申请日：2020-10-06

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： WEI-YI WEI

IPC: G06F13/24 ,  H04L12/931

Abstract: An electronic device, a network switch and an interrupt transmitting and receiving method are provided. The electronic device includes a slave chip and a main chip. The slave chip is configured to generate a plurality of data segments and at least one interrupt message and includes an encoder. The encoder is configured to encode the data segments and the interrupt message to generate a digital data. The interrupt message is arranged between the data segments. The main chip, which is coupled to the slave chip, is configured to receive the digital data and includes a decoder and a control circuit. The decoder is configured to decode the digital data to obtain the data segments and the interrupt message. The control circuit is coupled to the decoder and is configured to process the interrupt message.

公开(公告)号：US20210089113A1

公开(公告)日：2021-03-25

申请号：US17115604

申请日：2020-12-08

Applicant: Intel Corporation

Inventor： Herbert Hum ,  Eric Sprangle ,  Doug Carmean ,  Rajesh Kumar

IPC: G06F1/3293 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  G06T1/20 ,  G06F1/3206 ,  G06F9/50 ,  G06F13/24 ,  G06F9/38 ,  G06F9/46 ,  G06F1/3228 ,  G06F1/20 ,  G06F1/3287 ,  G06F12/0875

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system

公开(公告)号：US10949367B2

公开(公告)日：2021-03-16

申请号：US16657718

申请日：2019-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anup Manohar Kaveri ,  Nischal Jain ,  Rohit Kumar Saraf ,  Samarth Varshney ,  Shwetang Singh ,  Vinayak Hanagandi ,  Srinivasa Rao Kola ,  Younjo Oh

IPC: G06F13/24 ,  G06F9/52

Abstract: A method for handling kernel services for interrupt routines in a multi-core processor in an electronic device. The method comprises receiving a first interrupt on a first core of the multi-core processor, wherein the first interrupt includes at least one kernel service request and at least one non-kernel service request. The method further determines whether a worker queue of the first core in empty and whether a kernel service lock for the at least one kernel service request is acquired by at least one second core of the multi-core processor, in response to determining that the worker queue of the first core is empty. The method further comprises executing the at least one non-kernel service request of the first interrupt on the first core. The pending kernel service request are queued in the worker queue based on whether worker queue is empty or not and availability of kernel lock.

公开(公告)号：US10929263B2

公开(公告)日：2021-02-23

申请号：US16188756

申请日：2018-11-13

Applicant: International Business Machines Corporation

Inventor： John Richard Paveza ,  Harry M Yudenfriend

IPC: G06F11/34 ,  G06F13/24 ,  G06F9/48 ,  G06F11/07

Abstract: In one example implementation according to an embodiment described herein, a computer-implemented method includes detecting input/output (I/O) interrupts for executing I/O operations occurring over a period of time. The method further includes calculating an I/O interrupt delay time (IIDT) for each I/O interrupt occurring during the period of time. The method further includes binning the IIDT for each I/O interrupt occurring during the period of time into one of a plurality of bins based on a value of the IIDT, each of the plurality of bins storing a count of IIDT values within a defined range. The method further includes determining a highest IIDT value. The method further includes identifying a performance degradation based at least on one of the count of IIDT values of each of the plurality of bins or the highest IIDT value. The method further includes implementing a corrective action to mitigate the performance degradation.

公开(公告)号：US20210042255A1

公开(公告)日：2021-02-11

申请号：US16556046

申请日：2019-08-29

Applicant: Sony Interactive Entertainment LLC

Inventor： Roelof Roderick Colenbrander

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/16 ,  A63F13/355 ,  G06F13/24

Abstract: A cloud gaming system includes a storage system and a compute system connected through a PCIe fabric. The compute system generates a command buffer for a read operation, writes the command buffer to storage system memory, and notifies the storage system about the command buffer. The storage system reads the command buffer in its memory and processes the command buffer to read requested data. In one embodiment, the storage system writes the requested data in the storage system memory and notifies the compute system about the requested data in the storage system memory, and the compute system reads the requested data from the storage system memory. In another embodiment, the storage system writes the requested data in the compute system memory and notifies the compute system about the requested data in the compute system memory, and the compute system reads the requested data from the compute system memory.