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81.发明授权System and method for an accuracy-enhanced DLL during a measure initialization mode 有权测量初始化模式期间精度增强型DLL的系统和方法公开(公告)号：US09571105B2
公开(公告)日：2017-02-14
申请号：US14566358
申请日：2014-12-10
发明人： Jongtae Kwak
CPC分类号： H03L7/0802 , G11C7/1072 , G11C7/222 , H03L7/0814 , H03L7/0818
摘要： A clock generator having a delay locked loop and a delay control circuit. The delay locked loop receives an input clock signal and adjusts an adjustable delay circuit to generate an output clock signal that is synchronized with received input clock signal. The delay control circuit coupled to the delay locked loop generates a control signal to initialize the delay measure operation to adjust the adjustable delay circuit, after comparing the phase difference of the input clock signal and the output clock signal. The delay control circuit further generates a start measure control signal to start measuring a delay applied to the measurement signal propagating through the adjustable delay circuit, and generates a stop measure control signal to stop the delay measurement of the measurement signal. The delay adjustment of the delay locked loop is then adjusted to apply the delay measurement when synchronizing the input and output clock signals.
摘要翻译： 一种具有延迟锁定环路和延迟控制电路的时钟发生器。 延迟锁定环接收输入时钟信号并调整可调延迟电路以产生与接收的输入时钟信号同步的输出时钟信号。 耦合到延迟锁定环的延迟控制电路在比较输入时钟信号和输出时钟信号的相位差之后，产生控制信号以初始化延迟测量操作以调整可调延迟电路。 延迟控制电路还产生开始测量控制信号，以开始测量延迟通过可调延迟电路传播的测量信号的延迟，并产生停止测量控制信号以停止测量信号的延迟测量。 然后调整延迟锁定环路的延迟调整，以在同步输入和输出时钟信号时应用延迟测量。
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82.发明授权Delay-locked loop arrangement and method for operating a delay-locked loop circuit 有权延迟锁定环路布置和操作延迟锁定环路的方法公开(公告)号：US09571080B2
公开(公告)日：2017-02-14
申请号：US14817446
申请日：2015-08-04
申请人： Synopsys, Inc.
发明人： Jan Grabinski
CPC分类号： H03K5/135 , H03K2005/00058 , H03L7/08 , H03L7/0802 , H03L7/0812 , H03L7/10
摘要： Delay-locked loop arrangement comprising a steering unit and a delay-locked loop circuit. The steering unit is configured to generate a reference clock signal and a main clock signal wherein the reference clock signal and the main clock signal feature a first frequency during a performance mode of operation. The reference clock signal and the main clock signal feature a second frequency being lower than the first frequency and a phase delay with respect to each other during a sleep mode of operation. The delay-locked loop circuit is configured to generate an error signal depending on a comparison of the reference clock signal and a feedback signal. Furthermore, the delay-locked loop circuit generates the feedback signal depending on the error signal and on the main clock signal.
摘要翻译： 延迟锁定环路布置包括转向单元和延迟锁定环路电路。 转向单元被配置为产生参考时钟信号和主时钟信号，其中参考时钟信号和主时钟信号在执行操作模式期间具有第一频率。 参考时钟信号和主时钟信号在睡眠操作模式期间具有低于第一频率的第二频率和相对于彼此的相位延迟。 延迟锁定环电路被配置为根据参考时钟信号和反馈信号的比较产生误差信号。 此外，延迟锁定环电路根据误差信号和主时钟信号产生反馈信号。
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公开(公告)号：US09559703B2
公开(公告)日：2017-01-31
申请号：US14613123
申请日：2015-02-03
CPC分类号： H03L7/08 , G06F1/06 , G06F1/10 , H04L12/6418
摘要： Provided herein are apparatus and methods for system ready in a clock distribution chip or system. In certain configurations, a communication system includes a clock generation circuit having a divider and phase control circuit to provide output clock signals. The communication system further includes a system ready circuit to provide a system ready signal indicative of whether all of the output clock signals are ready.
摘要翻译： 本文提供了用于在时钟分配芯片或系统中准备的系统的装置和方法。 在某些配置中，通信系统包括具有分频器和相位控制电路以提供输出时钟信号的时钟产生电路。 通信系统还包括系统就绪电路，以提供指示所有输出时钟信号是否准备就绪的系统就绪信号。
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公开(公告)号：US09553570B1
公开(公告)日：2017-01-24
申请号：US14566571
申请日：2014-12-10
发明人： Jagdeep Bal
IPC分类号： H03L7/06 , H03K5/1252 , H03B5/08 , H03B5/04
CPC分类号： H03K5/1252 , H03B5/04 , H03B5/1212 , H03B5/124 , H03B2200/009
摘要： An integrated circuit to remove jitter from a clock signal includes an integrated circuit die. The integrated circuit die includes a signal comparator. The signal comparator is configured to determine a frequency difference between a jittery input clock signal and a correction signal. A digital low pass filter is coupled to receive and filter the frequency difference and to provide a filtered output signal. A free running crystal-less oscillator produces a reference signal. A fractional output divider is coupled to the free running crystal-less oscillator and the digital low pass filter. The fractional output divider utilizes the filtered output signal to establish a value to divide the reference signal by to obtain a clean output clock signal. The clean output clock signal is fed back to the signal comparator and is used as the correction signal.
摘要翻译： 用于从时钟信号中去除抖动的集成电路包括集成电路管芯。 集成电路管芯包括信号比较器。 信号比较器被配置为确定抖动输入时钟信号和校正信号之间的频率差。 数字低通滤波器被耦合以接收和滤除频率差并提供经滤波的输出信号。 自由运行的无晶体振荡器产生参考信号。 分数输出分频器耦合到自由运行的无晶体振荡器和数字低通滤波器。 分数输出分频器利用滤波后的输出信号建立一个值，以分配参考信号以获得干净的输出时钟信号。 干净的输出时钟信号反馈到信号比较器，并用作校正信号。
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85.发明授权High-speed resistor-based charge pump for active loop filter-based phase-locked loops 有权基于高速电阻器的电荷泵，用于基于有源环路滤波器的锁相环公开(公告)号：US09543969B2
公开(公告)日：2017-01-10
申请号：US14961590
申请日：2015-12-07
CPC分类号： H03L7/085 , H03L7/0891
摘要： Techniques are described for increasing the speed of a resistor-based charge pump for an active loop filter-based phase-locked loop (PLL). The techniques may include placing a low-resistance discharge path between respective nodes of a current source and sink in a charge pump, and selectively activating the low-resistance discharge path when the charge pump is turned off. The low-resistance discharge path may have a resistance that is lower than the resistance of other current paths between the respective nodes in the charge pump (e.g., current paths formed by the resistors included in the current source and sink of the charge pump), thereby reducing the amount of time needed to reset the charge on the respective nodes when the charge pump is turned off. In this way, the speed of a resistor-based charge pump may be increased, thereby allowing the overall speed of an active filter-based PLL to be increased.
摘要翻译： 描述了用于增加用于基于有源环路滤波器的锁相环（PLL）的基于电阻器的电荷泵的速度的技术。 这些技术可以包括将电流源的各个节点之间的低电阻放电路径放置在电荷泵中，并且在电荷泵关闭时选择性地启动低电阻放电路径。 低电阻放电路径可以具有低于电荷泵中的各个节点之间的其它电流路径的电阻的电阻（例如，由电荷源的电流源和电荷泵中的电阻器形成的电流路径）， 从而减少当电荷泵关闭时复位各个节点上的电荷所需的时间量。 以这种方式，可以增加基于电阻器的电荷泵的速度，从而允许基于有源滤波器的PLL的总体速度增加。
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公开(公告)号：US09537493B2
公开(公告)日：2017-01-03
申请号：US14283702
申请日：2014-05-21
申请人： Robert Bosch GmbH
摘要： A phase lock loop circuit includes a phase detector, loop filter, voltage controlled oscillator, and a divider. The divider includes a controller and a memory that stores a lookup table of signal levels for a sinusoidal feedback signal. The divider receives an output signal from the voltage controlled oscillator and generates an output signal corresponding to the values in the lookup table in a predetermined order to generate a sinusoidal feedback signal. The divider generates a new output for each cycle of the output signal from the voltage controlled oscillator and enables PLL bandwidth that meets or exceeds a frequency of the reference signal.
摘要翻译： 锁相环电路包括相位检测器，环路滤波器，压控振荡器和分频器。 分频器包括控制器和存储器，其存储用于正弦反馈信号的信号电平的查找表。 分压器接收来自压控振荡器的输出信号，并以预定的顺序产生与查找表中的值对应的输出信号，以产生正弦反馈信号。 分压器为来自压控振荡器的输出信号的每个周期产生一个新的输出，并使得能够达到或超过参考信号频率的PLL带宽。
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公开(公告)号：US09537492B2
公开(公告)日：2017-01-03
申请号：US14745017
申请日：2015-06-19
申请人： ANALOG DEVICES, INC.
CPC分类号： H03L7/085
摘要： An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.
摘要翻译： 集成电路实现了锁相环（PLL）的至少一部分。 集成电路包括用于PLL的采样模拟环路滤波器。 环路滤波器包括用于接收表示参考时钟信号和第一时钟信号之间的相位差的信号的第一输入端，用于提供用于控制振荡器频率的频率控制信号的第一输出端，用于接收振荡器的时钟输入 环路定时时钟信号，用于控制环路滤波器的操作定时;以及数字控制输入，用于根据多个控制值配置环路滤波器的响应。 在一些示例中，环路滤波器包括通过可控开关耦合的电荷存储元件和用于在电荷存储元件之间传送电荷的控制电路，以产生环路滤波器的配置响应。
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公开(公告)号：US09520883B2
公开(公告)日：2016-12-13
申请号：US14834927
申请日：2015-08-25
申请人： FUJITSU LIMITED
发明人： Takayuki Shibasaki
摘要： A frequency detection circuit includes: a first comparison circuit configured to output a first comparison result produced by comparison between a second threshold value higher than a first threshold value; a second comparison circuit configured to output a second comparison result produced by comparison between a third threshold value lower than the first threshold value; a third comparison circuit configured to output a third comparison result produced by comparison between the input data, and the first threshold value at second timing of a second clock; a phase detector configured to determine in which one of the areas an edge of the input data is positioned among the three areas produced by dividing a phase in a one-bit width time into three areas; and a phase rotation detector configured to detect a rotation direction of the phase based on a change of a detection result in the phase detector.
摘要翻译： 频率检测电路包括：第一比较电路，被配置为输出通过比较高于第一阈值的第二阈值而产生的第一比较结果; 第二比较电路，被配置为输出比第一阈值低的第三阈值之间的比较产生的第二比较结果; 第三比较电路，被配置为输出在第二时钟的第二定时处的输入数据和第一阈值之间的比较产生的第三比较结果; 相位检测器，被配置为通过将一位宽度时间中的相位除以三个区域来确定输入数据的边缘在哪个区域中的哪个区域中; 以及相位旋转检测器，被配置为基于相位检测器中的检测结果的变化来检测相位的旋转方向。
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公开(公告)号：US09515669B2
公开(公告)日：2016-12-06
申请号：US15047778
申请日：2016-02-19
发明人： Prakash Reddy
CPC分类号： H03L7/103 , H03L7/087 , H03L7/093 , H03L7/0991
摘要： A digital phased lock loop includes a digital controlled oscillator configured to produce an output signal at a frequency. A phase comparator compares the output signal, or a signal derived therefrom, with a reference signal to produce a phase error signal. A first loop filter produces a first control signal for the digital controlled oscillator from an output of the phase comparator. A frequency error measuring circuit coupled to the output of the phase comparator produces a frequency error signal. A second loop filter produces a second control signal for the digital controlled oscillator from an output of the frequency error measuring circuit. A circuit combines the first and second control signals and provides the combined control signals to the digital controlled oscillator.
摘要翻译： 数字相位锁定环包括配置成以频率产生输出信号的数字控制振荡器。 相位比较器将输出信号或由其导出的信号与参考信号进行比较，以产生相位误差信号。 第一环路滤波器从相位比较器的输出产生数字控制振荡器的第一控制信号。 耦合到相位比较器的输出的频率误差测量电路产生频率误差信号。 第二环路滤波器从频率误差测量电路的输出产生数字控制振荡器的第二控制信号。 电路组合第一和第二控制信号，并将组合的控制信号提供给数字控制振荡器。
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90.发明授权Simultaneous accommodation of a low power signal and an interfering signal in a radio frequency (RF) receiver 有权在射频（RF）接收机中同时容纳低功率信号和干扰信号公开(公告)号：US09509351B2
公开(公告)日：2016-11-29
申请号：US13559745
申请日：2012-07-27
CPC分类号： H04B1/10 , H03L7/06 , H04B1/0028 , H04B1/28
摘要： A method includes providing a highly linear front end in a Radio Frequency (RF) receiver, implementing a high Effective Number of Bits (ENOB) Analog to Digital Converter (ADC) circuit in the RF receiver, and sampling, through the high ENOB ADC circuit, at a frequency having harmonics that do not coincide with a desired signal component of an input signal of the RF receiver to eliminate spurs within a data bandwidth of the RF receiver. The input signal includes the desired signal component and an interference signal component. The interference signal component has a higher power level than the desired signal component. The method also includes simultaneously accommodating the desired signal component and the interference signal component in the RF receiver based on an increased dynamic range of the RF receiver and the high ENOB ADC circuit provided through the highly linear front end and the high ENOB ADC circuit.
摘要翻译： 一种方法包括在射频（RF）接收机中提供高度线性的前端，实现RF接收机中的高有效位数（ENOB）模/数转换器（ADC）电路，并通过高ENOB ADC电路进行采样 ，其频率具有与RF接收机的输入信号的期望信号分量不一致的谐波，以消除RF接收机的数据带宽内的杂散。 输入信号包括期望的信号分量和干扰信号分量。 干扰信号分量具有比期望的信号分量更高的功率水平。 该方法还包括基于通过高线性前端和高ENOB ADC电路提供的RF接收机和高ENOB ADC电路的增加的动态范围，同时容纳RF接收机中的期望信号分量和干扰信号分量。
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