公开(公告)号：US20150154077A1

公开(公告)日：2015-06-04

申请号：US13475270

申请日：2012-05-18

Applicant: Gregory Matthew Marra ,  Christopher J. Marra

Inventor： Gregory Matthew Marra ,  Christopher J. Marra

IPC: G06F11/08 ,  G06F11/14 ,  H04L29/08

CPC classification number: G06F11/143 ,  G06F8/65 ,  G06F11/0709 ,  G06F11/0793 ,  H04L67/10 ,  H04L67/34 ,  H04L69/40

Abstract: A system and machine-implemented method for handling an unexpected error associated with an application are disclosed. The subject disclosure provides for sending, from a client running a client application, an instruction to an application server hosting a server application associated with the client application, detecting an unexpected error in response to the sent instruction, automatically requesting, from the application server, an updated version of application code for the client application in response to the detected unexpected error, receiving the updated version of application code and updating the client application using the updated version of application code.

Abstract translation: 公开了一种用于处理与应用相关联的意外错误的系统和机器实现的方法。 本发明提供从运行客户应用程序的客户端向托管与客户端应用程序相关联的服务器应用程序的应用服务器发送响应于所发送的指令的意外错误，从应用服务器自动请求， 用于响应于检测到的意外错误的客户端应用的应用代码的更新版本，接收应用代码的更新版本并使用应用代码的更新版本来更新客户端应用。

公开(公告)号：US09043655B2

公开(公告)日：2015-05-26

申请号：US13929216

申请日：2013-06-27

Applicant: FUJITSU LIMITED

Inventor： Takahiko Kimura

IPC: G06F11/08 ,  G06F11/10

CPC classification number: G06F11/08 ,  G06F11/1008

Abstract: An apparatus includes a first memory, a second memory, a processor configured to perform an initialization process including adding data that generates a first error to initialization data and storing the initialization data together with the added data in the first memory to initialize the first memory, and a controller configured to perform an exchanging process including, when a second error occurs in the second memory during reading or writing data from or to the second memory, copying the data stored in the second memory into the first memory and switching, using a selector, a memory for use in writing and reading data from the second memory to the first memory. The processor is configured to read data from the first memory and the second memory and detect a failure of the selector or a failure of the exchanging process depending on whether the first error occurs or not.

Abstract translation: 一种装置，包括第一存储器，第二存储器，处理器，被配置为执行初始化处理，包括将生成第一错误的数据添加到初始化数据，并将初始化数据与添加的数据一起存储在第一存储器中以初始化第一存储器， 以及控制器，被配置为执行交换处理，所述交换处理包括当在从所述第二存储器读取或写入数据的过程中在所述第二存储器中发生第二错误时将所述第二存储器中存储的数据复制到所述第一存储器中并使用选择器 ，用于将数据从第二存储器写入和读取到第一存储器的存储器。 处理器被配置为从第一存储器和第二存储器读取数据，并且根据是否发生第一错误来检测选择器的故障或交换过程的故障。

公开(公告)号：US09032263B2

公开(公告)日：2015-05-12

申请号：US13908291

申请日：2013-06-03

Applicant: Marvell World Trade Ltd.

Inventor： Xueshi Yang

IPC: G11C29/00 ,  G06F11/08 ,  G11C11/56 ,  H03M13/15 ,  H03M13/19 ,  H03M13/37 ,  H03M13/45 ,  H03M13/11

CPC classification number: G06F11/08 ,  G11C11/5642 ,  G11C29/00 ,  H03M13/1102 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/154 ,  H03M13/19 ,  H03M13/373 ,  H03M13/3746 ,  H03M13/451 ,  H03M13/458

Abstract: Embodiments herein provide data recovery techniques and configurations for solid state memory devices. For example, a method includes identifying a hard error associated with a cell of a solid state memory device, providing a location of the cell having the identified hard error to a decoder to recover data originally programmed to the cell, and recovering the data originally programmed to the cell using the decoder. Other embodiments may be described and/or claimed.

Abstract translation: 本文的实施例提供了用于固态存储器件的数据恢复技术和配置。 例如，一种方法包括识别与固态存储器设备的单元相关联的硬错误，向解码器提供具有所识别的硬错误的单元的位置，以恢复原始编程到该单元的数据，以及恢复原始编程的数据 使用解码器到单元。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09021315B1

公开(公告)日：2015-04-28

申请号：US14147886

申请日：2014-01-06

Applicant: Amazon Technologies, Inc.

Inventor： Bashuman Deb ,  Avichai M. Lissack

IPC: G06F11/00 ,  G06F11/08

CPC classification number: G06F11/08 ,  G06F9/45558 ,  G06F11/0712 ,  G06F11/0751

Abstract: Architectures and techniques for uploading virtual machine (VM) images to a network-accessible computing platform from a client device while simultaneously performing error detection of the VM images at the client device. One technique can include transmitting a request from the client device to upload VM images. The technique can further include receiving an application from the computing platform and using the application to reconstitute the VM images from a first stream at the client device while performing error detection. The technique also includes using the application to upload the VM images from a second stream at the client device to the computing platform while performing the error detection.

Abstract translation: 将虚拟机（VM）映像从客户端设备上传到网络可访问计算平台的架构和技术，同时在客户端设备上执行VM映像的错误检测。 一种技术可以包括从客户端设备发送请求以上传VM图像。 该技术可以进一步包括从计算平台接收应用程序，并使用应用程序在执行错误检测时从客户端设备的第一个流重建VM映像。 该技术还包括使用应用程序在执行错误检测时将VM映像从客户端设备的第二个流上传到计算平台。

公开(公告)号：US08996966B2

公开(公告)日：2015-03-31

申请号：US13957672

申请日：2013-08-02

Applicant: Kabushiki Kaisha Toshiba

Inventor： Teruyuki Matsuoka ,  Yukio Ishikawa ,  Tsuyoshi Ukyou ,  Fuying Yang ,  Toshihiko Kitazume

IPC: H03M13/00 ,  H03M13/15 ,  G06F11/08

CPC classification number: G06F11/08 ,  H03M13/1545

Abstract: According to one embodiment, an error correction device includes a syndrome processing unit, a generation unit, and a search processing unit. The syndrome processing unit generates a syndrome value based on received data. The generation unit generates t (t is a maximum number of correctable bits) coefficient values of an error position polynomial based on the syndrome value. The search processing unit calculates a root of the error position polynomial, with a concurrency of computation being equal to or greater than “2”, by using the coefficient values of the error position polynomial, when a number of error bits is not more than a predetermined value s (1

Abstract translation: 根据一个实施例，错误校正装置包括校正子处理单元，生成单元和搜索处理单元。 校正子处理单元基于接收到的数据生成校正子值。 生成单元基于校正子值生成误差位置多项式的t（t是可校正位的最大数）系数值。 搜索处理单元通过使用错误位置多项式的系数值，在错误位数不大于1的情况下，通过使用等于或大于“2”的计算并行计算错误位置多项式的根 预定值s（1 <= s

公开(公告)号：US20150067431A1

公开(公告)日：2015-03-05

申请号：US14012492

申请日：2013-08-28

Applicant: Landis+Gyr Technologies, LLC

Inventor： Stuart L. Haug ,  Damian Bonicatto

IPC: G06F11/08

CPC classification number: G06F11/08 ,  H04L1/1819 ,  H04L1/189

Abstract: In one or more embodiments, a data processing apparatus is configured to receive data symbols transmitted from one or more endpoint devices. Each of the data symbols is transmitted in a respective temporal position assigned for communication by one of the plurality of endpoints. The data processing apparatus is configured to recover data from two or more transmission(s)/retransmission(s) (of the same data) that are received in error and have different temporal positions. The corresponding data symbols in error are phase-aligned per a common reference point and energy is accumulated therefrom. The data processing apparatus discerns correct data values from the accumulated energy.

Abstract translation: 在一个或多个实施例中，数据处理设备被配置为接收从一个或多个端点设备发送的数据符号。 每个数据符号在分配给多个端点之一的通信的相应时间位置中发送。 数据处理装置被配置为从错误接收并具有不同时间位置的两个或多个（相同数据）的一个或多个传输/重传中恢复数据。 相应的数据符号错误地是根据公共参考点进行相位校准，并从中积累能量。 数据处理装置从累积的能量中识别正确的数据值。

公开(公告)号：US20150019938A1

公开(公告)日：2015-01-15

申请号：US14502399

申请日：2014-09-30

Applicant: Juniper Networks, Inc.

Inventor： Rasoul Mirzazadeh OSKOUY ,  Dennis C. FERGUSON ,  Hann-Hwan Ju ,  Raymond Marcelino Manese LIM ,  Pradeep S. SINDHU ,  Sreeram VEERAGANDHAM ,  Jeff ZIMMER ,  Michael M.Y. HUI

IPC: H04L12/741 ,  H04L29/06 ,  G06F11/08

CPC classification number: H04L45/74 ,  G06F11/08 ,  H04L1/0041 ,  H04L12/56 ,  H04L12/5601 ,  H04L29/06 ,  H04L45/00 ,  H04L45/20 ,  H04L45/60 ,  H04L47/6225 ,  H04L49/103 ,  H04L49/108 ,  H04L49/203 ,  H04L49/25 ,  H04L49/254 ,  H04L49/30 ,  H04L49/3009 ,  H04L49/3063 ,  H04L49/3081 ,  H04L49/555 ,  H04L49/602 ,  H04L49/608 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047 ,  H04L69/16 ,  H04L69/161 ,  H04L69/22 ,  H04L69/324 ,  H04L2012/5652 ,  H04L2012/5679 ,  H04Q11/0478

Abstract: A method and apparatus for in-line processing a data packet while routing the packet through a router in a system transmitting data packets between a source and a destination over a network including the router. The method includes receiving the data packet and pre-processing layer header data for the data packet as the data packet is received and prior to transferring any portion of the data packet to packet memory. The data packet is thereafter stored in the packet memory. A routing through the router is determined including a next hop index describing the next connection in the network. The data packet is retrieved from the packet memory and a new layer header for the data packet is constructed from the next hop index while the data packet is being retrieved from memory. The new layer header is coupled to the data packet prior to transfer from the router.

公开(公告)号：US08930599B2

公开(公告)日：2015-01-06

申请号：US14048388

申请日：2013-10-08

Applicant: Via Technologies, Inc.

Inventor： Jiin Lai ,  Buheng Xu ,  Jinkuan Tang

IPC: G06F13/12 ,  G06F13/38 ,  G06F13/00 ,  G06F11/08

CPC classification number: G06F13/385 ,  G06F11/08 ,  G06F13/00 ,  G06F13/12

Abstract: A data transmission system and method are provided. The data transmission method receives a second format data packet sent by a host; decodes the second format data packet sent by the host, and translating the decoded second format data packet into a first format data packet; transmits the first format data packet to a first device; receives a transmission response sent by the first device in response to the first format data packet, determines whether to transmit the transmission response to the host, and performs a re-try flow when the transmission response does not need to be transmitted to the host. Preferably, a data transmission rate of the first device is slower than that of a second device, and the data transmission system is backward compatible to the first device, and the second format data packet is consistent with the second device.

Abstract translation: 提供了一种数据传输系统和方法。 数据传输方法接收主机发送的第二格式数据包; 解码由主机发送的第二格式数据分组，并将解码的第二格式数据分组转换为第一格式数据分组; 将第一格式数据分组发送到第一设备; 响应于第一格式数据分组接收由第一设备发送的传输响应，确定是否向主机发送传输响应，并且当传输响应不需要发送到主机时执行重试流程。 优选地，第一设备的数据传输速率比第二设备的数据传输速率慢，并且数据传输系统向后兼容于第一设备，并且第二格式数据分组与第二设备一致。

公开(公告)号：US20140325322A1

公开(公告)日：2014-10-30

申请号：US14330797

申请日：2014-07-14

Applicant: Renesas Electronics Corporation

Inventor： Shunichi KAERIYAMA

IPC: G06F11/08

CPC classification number: G06F11/08 ,  G01R31/265 ,  G01R31/302 ,  G06K19/0723 ,  H01L23/5227 ,  H01L25/16 ,  H01L25/162 ,  H01L25/167 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H03F3/085 ,  H03F3/189 ,  H03F3/24 ,  H03F3/45475 ,  H03F3/45479 ,  H03F2203/45544 ,  H03F2203/45621 ,  H03K17/0828 ,  H03K17/567 ,  H03K17/689 ,  H03K17/691 ,  H03K17/78 ,  H03K2017/0806 ,  H04B5/0012 ,  H04B5/0075 ,  H04B5/0081 ,  H04L25/0266 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor integrated circuit includes a first transmission circuit generating and outputting a first transmission signal reflecting a first data signal supplied from outside, a first reception circuit reproducing the first data signal based on a first reception signal, a first isolation element isolating the first transmission circuit from the first reception circuit and transmitting the first transmission signal as the first reception signal, a second transmission circuit generating and outputting a second transmission signal reflecting a second data signal supplied from outside, a second reception circuit reproducing the second data signal based on a second reception signal, a second isolation element isolating the second transmission circuit from the second reception circuit and transmitting the second transmission signal as the second reception signal, and a third transmission circuit generating and outputting a third transmission signal reflecting the second data signal.

Abstract translation: 半导体集成电路包括：第一发送电路，生成并输出反映从外部提供的第一数据信号的第一发送信号，第一接收电路，基于第一接收信号再现第一数据信号;第一隔离元件，隔离第一发送电路 从第一接收电路发送第一发送信号作为第一接收信号，生成并输出反映从外部提供的第二数据信号的第二发送信号的第二发送电路，基于第二接收电路再生第二数据信号的第二接收电路 接收信号，第二隔离元件，将第二发送电路与第二接收电路隔离，并发送第二发送信号作为第二接收信号;第三发送电路，生成并输出反映第二数据信号的第三发送信号。

公开(公告)号：US08875004B2

公开(公告)日：2014-10-28

申请号：US12668346

申请日：2007-07-10

Applicant: Kazunori Washio ,  Satoshi Udou ,  Yasuto Kanayama

Inventor： Kazunori Washio ,  Satoshi Udou ,  Yasuto Kanayama

IPC: G06F11/08 ,  H04L1/00 ,  G06F11/36

CPC classification number: H04L1/0084 ,  H04L1/0061

Abstract: A transmitting apparatus included in a communication system that performs message communication using an error detection code with a receiving apparatus, the transmitting apparatus includes a transmission interval determining means that, based on a parameter related to a transmission error non-detection probability of a message per time, a data length of the message, and a code length of the error detection code used for the message, determines a transmission interval for transmitting the message, so that the transmission error non-detection probability of the message satisfies a condition related to a transmission error non-detection probability included in the parameter, wherein the message is transmitted to the receiving apparatus, based on the transmission interval determined by the transmission interval determining means.

Abstract translation: 一种发送装置，包括在通过使用与接收装置的错误检测码进行消息通信的通信系统中，所述发送装置包括：发送间隔确定装置，根据与所述消息的发送错误非检测概率相关的参数， 时间，消息的数据长度和用于消息的错误检测码的代码长度确定用于发送消息的传输间隔，使得消息的传输错误非检测概率满足与 包括在参数中的传输错误非检测概率，其中基于由传输间隔确定装置确定的传输间隔将消息发送到接收设备。