BUS CONFIGURATION SYSTEM AND METHOD THEREOF
    1.
    发明公开

    公开(公告)号:US20240311327A1

    公开(公告)日:2024-09-19

    申请号:US18426261

    申请日:2024-01-29

    IPC分类号: G06F13/42 G06F1/10 G06F13/40

    摘要: A bus configuration system includes a plurality of driver integrated circuits (ICs) coupled sequentially on a daisy chain, and a bus controller coupled to the plurality of driver ICs. Each driver IC includes a plurality of ports. The bus controller is used to generate a port definition code for configuring each port of the each driver IC. The bus controller includes a clock output port used to output a clock signal and a data output port used to output a data signal. When a port of the plurality of ports detects the clock signal, the port is configured as a clock input port.

    ELECTRONIC DEVICE HAVING MULTIPLE SPEAKERS CONTROLLED BY A SINGLE FUNCTIONAL CHIP

    公开(公告)号:US20240155292A1

    公开(公告)日:2024-05-09

    申请号:US18079011

    申请日:2022-12-12

    摘要: An electronic device includes two speakers, a single functional chip, a parameter extraction circuit, an audio processing module, a gain adjusting circuit and a current detecting unit. The current detecting unit is disposed in the functional chip for detecting the driving current of the two speakers. The functional chip provides the driving voltage of the two speakers based on an output signal and converts the analogue current/voltages of the two speakers into digital current/voltages. The parameter extraction circuit acquires the parameter of each speaker based on the digital current/voltages. The audio processing module acquires the gains of various physical quantities based on the parameter of each speaker and determines the final gain of each physical quantity. The gain adjusting circuit provides the output signal by adjusting the gain of an input signal based on the final gain of each physical quantity.

    Buck Converter with Quick Response Mechanism and Method Thereof

    公开(公告)号:US20230127211A1

    公开(公告)日:2023-04-27

    申请号:US17684393

    申请日:2022-03-01

    发明人: Yung-Jen Chen

    IPC分类号: H02M3/158 H02M1/00

    摘要: A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of on-time generators, a plurality of OR gates coupled to the corresponding on-time generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each on-time generator is coupled to the interleaving logic circuit, an input node and the output node. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.

    Voltage converter controller and voltage converter circuit

    公开(公告)号:US09859783B1

    公开(公告)日:2018-01-02

    申请号:US14075432

    申请日:2013-11-08

    摘要: A voltage converter controller, adapted to a voltage converter circuit, includes a power switch controller and a dead-time determining circuit. The power switch controller receives a PWM signal and outputs a high-side control signal and a low-side control signal accordingly to control the conduction and cut-off of a high-side power switch and a low-side power switch respectively. When the power switch controller starts to control the low-side power switch cut-off, after a first dead-time, the power switch controller starts to control the high-side power switch conducting. The dead-time determining circuit detects a current of the low-side power switch to be larger or smaller than a threshold current when the low-side power switch is conducted, and determines the first dead-time to be a first value or a second value accordingly.

    VOLTAGE CONVERTER CONTROLLER AND VOLTAGE CONVERTER CIRCUIT

    公开(公告)号:US20170366080A1

    公开(公告)日:2017-12-21

    申请号:US14075432

    申请日:2013-11-08

    IPC分类号: H02M1/088 H02M3/156 H02M1/00

    摘要: A voltage converter controller, adapted to a voltage converter circuit, includes a power switch controller and a dead-time determining circuit. The power switch controller receives a PWM signal and outputs a high-side control signal and a low-side control signal accordingly to control the conduction and cut-off of a high-side power switch and a low-side power switch respectively. When the power switch controller starts to control the low-side power switch cut-off, after a first dead-time, the power switch controller starts to control the high-side power switch conducting. The dead-time determining circuit detects a current of the low-side power switch to be larger or smaller than a threshold current when the low-side power switch is conducted, and determines the first dead-time to be a first value or a second value accordingly.

    Control circuit and method of a power converter

    公开(公告)号:US09654011B2

    公开(公告)日:2017-05-16

    申请号:US14695761

    申请日:2015-04-24

    发明人: Isaac Y. Chen

    IPC分类号: H02M3/335 H02M1/00 H02M1/32

    摘要: A feedback signal stabilized by a capacitor and related to an output voltage of a power converter is used to acquire the output power information of the power converter, and a control circuit uses a second clock not related to the switching frequency of the power converter to count a duration time of the feedback signal being higher than a threshold. When the duration time is higher than a preset time, an abnormal output power of the power converter is distinguished and the power converter will be turned off. The feedback signal will not vary severely even if the output terminal of the power converter is interfered, and the counted duration time will not be influenced when the switching frequency is changing caused by a load changing.

    Power off delay circuit and method, and audio system with power off delay
    10.
    发明授权
    Power off delay circuit and method, and audio system with power off delay 有权
    断电延时电路及方法,以及具有断电延时的音响系统

    公开(公告)号:US09219352B2

    公开(公告)日:2015-12-22

    申请号:US14165406

    申请日:2014-01-27

    IPC分类号: H02B1/24 H04R3/00

    摘要: A power off delay circuit includes a switch connected between an external power input terminal and an internal power supply terminal, a capacitor connected to the internal power supply terminal, and a hysteresis comparator to switch the switch according to the voltages of the external power input terminal and the internal power supply terminal. During on-time of the switch, the external power input terminal is connected to the internal power supply terminal and the capacitor can be charged by the external power source. When the switch is off, the capacitor provides electric power for an internal circuit. Application of the power off delay circuit to an audio system may eliminate the turn-off pops of the audio system.

    摘要翻译: 断电延迟电路包括连接在外部电源输入端子和内部电源端子之间的开关,连接到内部电源端子的电容器和滞后比较器,用于根据外部电力输入端子的电压来切换开关 和内部电源端子。 在接通时,外部电源输入端子连接到内部电源端子,电容器可以通过外部电源充电。 当开关关闭时,电容为内部电路提供电力。 将断电延迟电路应用于音频系统可以消除音频系统的关闭声音。