公开(公告)号：US07627130B2

公开(公告)日：2009-12-01

申请号：US09047252

申请日：1998-03-24

申请人： Pascal Mellot

发明人： Pascal Mellot

IPC分类号： H03G3/00

CPC分类号： H03G3/3026 ,  H03G3/001

摘要： A circuit for processing broadcast signals that includes circuitry for receiving and processing broadcast signals which contain audio information and providing a first audio signal, and circuitry for controlling the amplitude of a received second audio signal in response to a first control signal, and providing a third audio signal wherein the circuit further comprises circuitry that receives the first audio signal and provides the second audio signal for automatically limiting the amplitude of the first audio signal in response to at least one reference signal.

摘要翻译： 一种用于处理广播信号的电路，包括用于接收和处理包含音频信息并提供第一音频信号的广播信号的电路，以及用于响应于第一控制信号控制所接收的第二音频信号的幅度的电路，以及提供第三 音频信号，其中电路还包括接收第一音频信号并提供第二音频信号的电路，用于响应于至少一个参考信号自动限制第一音频信号的幅度。

公开(公告)号：US6145077A

公开(公告)日：2000-11-07

申请号：US645897

申请日：1996-05-14

申请人： Nathan Mackenzie Sidwell ,  Catherine Louise Barnaby

发明人： Nathan Mackenzie Sidwell ,  Catherine Louise Barnaby

IPC分类号： G06F9/305 ,  G06F7/76 ,  G06F9/30 ,  G06F9/308 ,  G06F9/315 ,  G06F9/38 ,  G06F7/00

CPC分类号： G06F7/76 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3885

摘要： A computer and a method of operating a computer is disclosed which allow manipulation of data values in the context of the execution of so-called "packed instructions". Packed instructions are carried out on packed operands. A packed operand comprises a data string consisting of a plurality of sub-strings, each defining a particular data value or object. The invention relates to a restructuring instruction which allows objects to be reorganized within a data string thereby minimizing loading and storing operations to memory.

摘要翻译： 公开了一种计算机和操作计算机的方法，其允许在执行所谓的“打包指令”的上下文中操纵数据值。 打包指令在打包操作数上执行。 打包操作数包括由多个子串组成的数据串，每个子串定义特定的数据值或对象。 本发明涉及一种重组指令，其允许在数据串中重新组织对象，从而最小化对存储器的加载和存储操作。

公开(公告)号：US6125416A

公开(公告)日：2000-09-26

申请号：US960757

申请日：1997-10-29

申请人： Robert Warren

发明人： Robert Warren

IPC分类号： G06F11/22 ,  G01R31/3185 ,  G06F11/36 ,  G06F15/17

CPC分类号： G06F11/3656 ,  G01R31/318572

摘要： A single chip integrated circuit device includes a bus system for effecting communication of parallel data on chip, functional circuitry connected to the bus system for executing an operation in response to parallel data received from the bus system, an external port, and a serial to parallel data packet converter interconnecting the parallel bus system and the external port. The external port includes a serial data input connector and a serial data output connector for supplying serial data packets between an external device and the integrated circuit device. The serial data packets each include a packet identifier indicating the length of the data packet and information defining an operation to be executed by the functional circuitry. The serial to parallel data packet converter is operable to read the packet identifier to determine the length of serial packets which are input through the port and to convert them into parallel data for supply in a forward direction to the bus system, such that if the serial data packet has a length which exceeds the bus width, the serial data packet is converted into successive sets of parallel data and placed sequentially on the bus system. The serial to parallel converter further includes flow control logic for indicating that it is ready to receive a subsequent data packet by transmitting a flow control signal in the reverse direction, and for requesting access to the bus system when the parallel data is ready to be output to the functional circuitry. In this device, the serial to parallel conversion of the serial packets into parallel data is effected without involving the functional circuitry, and the parallel data causes the functional circuitry to execute an operation dependent on the information contained in the serial packets from which it has been converted.

摘要翻译： 单芯片集成电路装置包括用于实现芯片上并行数据通信的总线系统，连接到总线系统的功能电路，用于响应从总线系统接收的并行数据执行操作，外部端口和串行到并行 数据包转换器将并行总线系统和外部端口互连。 外部端口包括串行数据输入连接器和串行数据输出连接器，用于在外部设备和集成电路设备之间提供串行数据包。 串行数据分组各自包括指示数据分组的长度的分组标识符和定义要由功能电路执行的操作的信息。 串行到并行数据分组转换器可操作以读取分组标识符以确定通过端口输入的串行分组的长度并将其转换为并行数据，以向前向方向供应到总线系统，使得如果串行 数据包的长度超过总线宽度，串行数据包被转换成连续的并行数据集，并且顺序放置在总线系统上。 串行到并行转换器还包括流控制逻辑，用于指示其准备好通过在相反方向上发送流控制信号来接收后续数据分组，并且当并行数据准备输出时请求对总线系统的访问 到功能电路。 在该装置中，将串行分组串行到并行转换成并行数据，而不涉及功能电路，并行数据使功能电路根据包含在已经被串行数据包的串行数据包中的信息执行操作 转换

公开(公告)号：US6031983A

公开(公告)日：2000-02-29

申请号：US28415

申请日：1998-02-24

申请人： Geoff Barrett

发明人： Geoff Barrett

IPC分类号： G06F19/00 ,  G06F17/50 ,  G06F17/11

CPC分类号： G06F17/504

摘要： A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system. The processing system comprises a logical device for transforming the transition functions of the system into constraints on the reverse model, and a parameterization processor for applying a parameterization of the constraints to the estimate of transition functions of reverse system to form transition functions of the reverse model.

摘要翻译： 用于合成系统的反向模型的装置包括存储表示系统的转换功能的位的第一存储器，存储表示反向模型的转换功能的估计的位的第二存储器和处理系统。 处理系统包括用于将系统的过渡功能转换为反向模型的约束的逻辑设备，以及参数化处理器，用于将约束的参数化应用于反向系统的转换函数的估计，以形成反向模型的转换函数 。

公开(公告)号：US5946705A

公开(公告)日：1999-08-31

申请号：US735474

申请日：1996-10-23

申请人： Peter Cumming ,  Richard Grisenthwaite

发明人： Peter Cumming ,  Richard Grisenthwaite

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F9/3806 ,  G06F12/0802

摘要： A cache memory comprises a CAM and a data RAM, the CAM has an associate input and a write input, the associate input being connected to selection circuitry to select write data or associate data so that an associate operation can be effected in parallel with a write operation using the same data to control validation of the write input.

摘要翻译： 高速缓冲存储器包括CAM和数据RAM，CAM具有关联输入和写入输入，所述关联输入连接到选择电路以选择写入数据或关联数据，使得可以与写入并行地实现关联操作 操作使用相同的数据来控制写入输入的验证。

公开(公告)号：US5884069A

公开(公告)日：1999-03-16

申请号：US661077

申请日：1996-06-10

申请人： Nathan M. Sidwell

发明人： Nathan M. Sidwell

IPC分类号： G06F7/57 ,  G06F9/302 ,  G06F9/305 ,  G06F15/78

CPC分类号： G06F7/57 ,  G06F15/8076 ,  G06F9/30014 ,  G06F9/30029 ,  G06F9/30036 ,  G06F2207/382

摘要： There is disclosed a computer and a method of operating a computer to allow combination of data values in the context of the execution of so-called "packed instructions". A data string comprising a certain number of sub-strings representing discrete data values and which are not independently addressable is held in a source register store. A combining instruction which operates to carry out a polyadic operation on at least some of the sub-strings to generate a result sub-string is then executed.A result data string comprising said result sub-string is loaded into a destination register. These "combining" instructions have the advantage that they are general purpose instructions which can be used in a plurality of different situations. The instructions are particularly useful in a packed arithmetic environment.

摘要翻译： 公开了一种计算机和操作计算机以允许在执行所谓的“打包指令”的上下文中组合数据值的方法。 包括表示离散数据值并且不能独立寻址的一定数量的子串的数据串被保存在源寄存器存储器中。 然后执行对至少一些子串执行多项式操作以产生结果子串的组合指令。 包括所述结果子串的结果数据串被加载到目的地寄存器中。 这些“组合”指令的优点在于它们是可以在多种不同情况下使用的通用指令。 指令在打包运算环境中特别有用。

公开(公告)号：US5859790A

公开(公告)日：1999-01-12

申请号：US649779

申请日：1996-05-17

申请人： Nathan Mackenzie Sidwell

发明人： Nathan Mackenzie Sidwell

IPC分类号： G06F9/305 ,  G06F7/76 ,  G06F9/30 ,  G06F9/308 ,  G06F9/34 ,  G06F17/16 ,  G06F9/00

CPC分类号： G06F7/76 ,  G06F17/16 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30036

摘要： A computer instruction is provided which replicates a bit sequence to generate a data string consisting only of a plurality of the replicated bit sequences. The computer instruction allows this to be done in a register store having a predetermined bit capacity addressable by a single address. The computer instruction is useful in the context of packed arithmetic instructions, where it is often desirable to combine each of a set of objects arithmetically or logically with a common object. A computer and a method of operating a computer using the instruction are described.

摘要翻译： 提供了一种计算机指令，其复制比特序列以生成仅由多个复制比特序列组成的数据串。 计算机指令允许在具有可由单个地址寻址的预定位容量的寄存器存储器中完成该操作。 计算机指令在打包运算指令的上下文中是有用的，其中通常期望将一组对象的算术或逻辑与公共对象组合。 描述了使用该指令来操作计算机的计算机和方法。

公开(公告)号：US5859789A

公开(公告)日：1999-01-12

申请号：US677837

申请日：1996-07-10

申请人： Nathan M. Sidwell

发明人： Nathan M. Sidwell

IPC分类号： G06F7/544 ,  G06F9/302 ,  G06F15/78

CPC分类号： G06F9/30014 ,  G06F15/8076 ,  G06F7/5443 ,  G06F9/30036

摘要： There is disclosed an arithmetic unit which allows a combined multiply-add operation to be carried out in response to execution of a single computer instruction. This is particularly useful in a packed arithmetic environment, when a operand comprises a plurality of packed objects and the intention is to carry out the same arithmetic operation on respective pairs of objects in different operands. There is also provided a computer and a method of operating a computer to effect the combined multiply-add operation.

摘要翻译： 公开了一种算术单元，其允许响应于单个计算机指令的执行而执行组合乘法运算。 这在打包运算环境中特别有用，当操作数包括多个打包对象时，意图是对不同操作数中的各对物体执行相同的算术运算。 还提供了一种计算机和一种操作计算机来实现组合乘法运算的方法。

公开(公告)号：US5818362A

公开(公告)日：1998-10-06

申请号：US616521

申请日：1996-03-19

申请人： Christopher P. H. Walker

发明人： Christopher P. H. Walker

IPC分类号： G06F11/10 ,  H03M5/18 ,  H03M7/14 ,  H04L25/49 ,  H03M5/16

CPC分类号： H03M5/18 ,  H04L25/4925

摘要： A method of encoding a five bit symbol into a four trit code word is disclosed, comprising defining out of forty-eight combinations of four trit code words three groups, each group containing sixteen code words, each code word within a group having a Hamming distance of at least two from any other code word in the group, and each code word being associated with a particular combination of four bits selected from said five bit symbol. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

摘要翻译： 公开了一种将五位符号编码成四字代码字的方法，包括定义四个代码字三组的四十八个组合，每组包含十六个代码字，组中的每个代码字具有汉明距离 至少两个来自组中的任何其他码字，并且每个码字与从所述五位符号中选择的四位的特定组合相关联。 还公开了一种类似的解码方法。 公开了用于执行编码和解码的装置。

公开(公告)号：US5812121A

公开(公告)日：1998-09-22

申请号：US397840

申请日：1995-03-02

申请人： Peter William Hughes

发明人： Peter William Hughes

IPC分类号： H04N9/64 ,  G05F3/24 ,  H03K5/151 ,  H03K17/042 ,  H03K17/16 ,  H03K19/0175 ,  H03K19/0948 ,  H03M1/66

CPC分类号： G05F3/24 ,  H03K17/04206 ,  H03K17/167 ,  H03K5/151

摘要： An output current unit comprises a cascode circuit having a first transistor connected between a voltage supply line and complementary outputs. Second and third transistors are controlled by inverter circuitry having parallel conducting paths between an output node and a ground line, the parallel conducting paths having different current carrying capacity with control circuitry to switch the stronger of the current carrying paths.

摘要翻译： 输出电流单元包括具有连接在电压供应线和互补输出之间的第一晶体管的共源共栅电路。 第二和第三晶体管由在输出节点和接地线之间具有并联导电路径的反相器电路控制，并联导电路径具有与控制电路不同的载流能力，以切换电流承载路径中较强的电流。