公开(公告)号：US6144640A

公开(公告)日：2000-11-07

申请号：US920256

申请日：1997-08-28

Applicant: Robert Simpson ,  Neil Richards ,  Peter Thompson ,  Pascal Moniot ,  Marcello Coppola ,  Pierre Dumas ,  Thierry Grenot ,  David Mouen Makoua

Inventor： Robert Simpson ,  Neil Richards ,  Peter Thompson ,  Pascal Moniot ,  Marcello Coppola ,  Pierre Dumas ,  Thierry Grenot ,  David Mouen Makoua

IPC: H04Q3/00 ,  H04L12/56 ,  H04Q11/04

CPC classification number: H04L12/5601 ,  H04L49/108 ,  H04L49/1553 ,  H04L49/255 ,  H04Q11/0478 ,  H04L2012/563 ,  H04L2012/5647 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5681

Abstract: An ATM routing switch for bidirectional transmission of at least two types of cell, one type accepting variable bit rate of transmission and a second type accepting some loss of cells in transmission, includes first reserve buffer capacity for cells of the first type, a second reserve buffer capacity for cells of said second type and control circuitry for generating a flow control signal (FCT) if a predetermined threshold for the first buffer capacity is reached by input of cells of said first type, and discarding input cells of said second type if a predetermined threshold for said second buffer capacity has been reached by input of cells of said second type.

Abstract translation: 用于至少两种类型的小区的双向传输的ATM路由交换机，接收可变比特率传输的一种类型和接收传输中的小区的一些丢失的第二类型，包括第一种类型的小区的第一预备缓冲器容量，第二种储备 如果通过所述第一类型的单元的输入达到用于第一缓冲器容量的预定阈值，则产生流控制信号（FCT）的所述第二类型的单元的缓冲器容量和控制电路，以及丢弃所述第二类型的输入单元，如果 通过输入所述第二类型的单元已经达到了所述第二缓冲器容量的预定阈值。

公开(公告)号：US6134512A

公开(公告)日：2000-10-17

申请号：US979450

申请日：1997-11-24

Applicant: Geoff Barrett

Inventor： Geoff Barrett

IPC: G06F19/00 ,  G06F17/50 ,  G06G7/62

CPC classification number: G06F17/504

Abstract: A system for representing a physical environment comprises a first store for holding a set of state bits, a second store for holding a set of input bits, an input device for inputting a set of initial states of said state bits into said first store, means for implementing a set of state transition functions for manipulating said input bits and said state bits, and means for generating input bits satisfying a set of constrains representing restrictions on the physical environment.

Abstract translation: 用于表示物理环境的系统包括用于保存一组状态位的第一存储器，用于保存一组输入位的第二存储器，用于将所述状态位的一组初始状态输入到所述第一存储器中的输入装置， 用于实现用于操纵所述输入比特和所述状态比特的一组状态转换功能，以及用于生成满足表示对所述物理环境的限制的一组约束的输入比特的装置。

公开(公告)号：US6100905A

公开(公告)日：2000-08-08

申请号：US660731

申请日：1996-06-06

Applicant: Nathan Mackenzie Sidwell

Inventor： Nathan Mackenzie Sidwell

IPC: G09G5/00 ,  G06F7/76 ,  G06F9/308 ,  G06T3/40 ,  G09G5/02 ,  G09G5/377 ,  G09G5/39 ,  G06F9/00

CPC classification number: G06F7/76 ,  G06F9/30018 ,  G09G5/024

Abstract: A computer instruction is described which expands compressed font information to provide an expanded format suitable for driving a display for example. The expansion is carried out by identifying a bit string having at least one bit sequence, selecting each bit of the bit sequence and replicating each selected bit at a plurality of adjacent locations. This is carried out in a register store having a predetermined bit capacity addressable by a single address. The instruction is particularly useful for generating background or foreground font information for driving a display.

Abstract translation: 描述了一种计算机指令，其扩展了压缩字体信息以提供适合于例如驱动显示器的扩展格式。 通过识别具有至少一个比特序列的比特串来进行扩展，选择比特序列的每个比特并在多个相邻的位置复制每个选择的比特。 这在具有可通过单个地址寻址的预定位容量的寄存器存储器中进行。 该指令对于生成用于驱动显示器的背景或前景字体信息特别有用。

公开(公告)号：US6088822A

公开(公告)日：2000-07-11

申请号：US959890

申请日：1997-10-29

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/3185 ,  G06F11/22

CPC classification number: G01R31/318572

Abstract: There is disclosed an integrated circuit comprising a test access port controller having a first mode of operation in which it is connectable to test logic to effect communication of serial test data and the control of an incoming clock signal, and a second mode of operation in which a data adaptor is connected to input and output pins via the test access port controller, the data adaptor being supplied with parallel data and control signals from on-chip functional circuitry and converting such parallel data and control signals into a sequence of serial bits including flow control bits.

Abstract translation: 公开了一种集成电路，其包括具有第一操作模式的测试访问端口控制器，其中可连接到测试逻辑以实现串行测试数据的通信和对输入时钟信号的控制;以及第二操作模式，其中 数据适配器通过测试访问端口控制器连接到输入和输出引脚，数据适配器被提供有来自片上功能电路的并行数据和控制信号，并将这样的并行数据和控制信号转换成包括流的串行位序列 控制位。

公开(公告)号：US6009508A

公开(公告)日：1999-12-28

申请号：US938242

申请日：1997-09-26

Applicant: Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

Inventor： Michael David May ,  Andrew Craig Sturges ,  Nathan Mackenzie Sidwell

IPC: G06F9/30 ,  G06F13/00

CPC classification number: G06F9/30167 ,  G06F9/30149 ,  G06F9/30163 ,  G06F9/30178 ,  G06F9/3816

Abstract: A computer system has instructions which have a reduction in the number of address bits relative to the number of data items that may be held during instruction execution. The instruction set comprises selectable instructions, a plurality of the instructions each including one set of bit locations identifying an operation to be carried out by execution of the instruction and a second set of bit locations to identify an address of a data storage location for use in execution of the instruction. The computer system further includes a plurality of addressable data storage locations for holding simultaneously a plurality of data values during execution of a sequence of instructions, with at least one of the data storage locations comprising a multi-value store requiring a single address in an instruction and arranged to hold a plurality of data values simultaneously on a first-in, first-out basis. This therefore increases the number of data values that can be held in relation to the number of addresses that can be identified by the second set of bit locations.A method of executing a succession of instructions in a computer system is also described.

Abstract translation: 计算机系统具有相对于在指令执行期间可能保持的数据项的数量减少地址位数的指令。 指令集包括可选择的指令，多个指令各自包括标识要通过执行指令执行的操作的一组比特位置和第二组比特位置，以识别数据存储位置的地址，以用于 执行指令。 计算机系统还包括多个可寻址数据存储位置，用于在执行指令序列期间同时保持多个数据值，其中至少一个数据存储位置包括要求指令中的单个地址的多值存储 并且被安排成以先入先出的方式同时保存多个数据值。 因此，这增加了可以相对于可由第二组位位置识别的地址数量来保持的数据值的数量。 还描述了在计算机系统中执行一系列指令的方法。

公开(公告)号：US5961637A

公开(公告)日：1999-10-05

申请号：US493103

申请日：1995-06-21

Applicant: Andrew C. Sturges ,  Nathan M. Sidwell

Inventor： Andrew C. Sturges ,  Nathan M. Sidwell

IPC: G06F9/32 ,  G06F9/38

CPC classification number: G06F9/3804 ,  G06F9/3842

Abstract: A computer system for executing branch instructions and a method of executing branch instructions are described. Tow instruction fetchers respectively fetch a sequence of instructions from memory for execution and a sequence of instructions commencing from a target location identified by a set branch instruction in a sequence of instructions being executed. When an effect branch signal is generated, the target instructions are next executed, and the fetcher which was fetching the instructions for execution commences fetching of the target instructions. The effect branch signal is generated separately from the set branch instruction. In another aspect, the effect branch signal is generated on execution of a conditional effect branch instruction, located at the point in the instruction sequence where the branch is to be taken.

Abstract translation: 描述用于执行分支指令的计算机系统和执行分支指令的方法。 牵引指令抓取器分别从用于执行的存储器中提取指令序列，以及从由执行的指令序列中的设置转移指令识别的目标位置开始的指令序列。 当产生效果分支信号时，接下来执行目标指令，并且获取执行指令的获取器开始获取目标指令。 效果分支信号与设定的分支指令分开产生。 在另一方面，效果分支信号是在执行位于要采用分支的指令序列中的点处的条件效果分支指令时产生的。

公开(公告)号：US5892466A

公开(公告)日：1999-04-06

申请号：US616522

申请日：1996-03-19

Applicant: Christopher P. H. Walker

Inventor： Christopher P. H. Walker

IPC: G06F11/10 ,  H03M5/18 ,  H03M7/00 ,  H03M7/14 ,  H04L1/00 ,  H04L25/49 ,  H03M5/16

CPC classification number: H04L25/4925 ,  H03M5/18

Abstract: A method of encoding first and second symbols each having n binary bits into first and second code words each having n-1 ternary trits is disclosed. The method involves using a preselected bit from each of the first and second symbols to determine which one of at least two groups of code words comprising n-1 trits is used for encoding. An analogous method of decoding is also disclosed. Apparatus for performing the encoding and decoding is disclosed.

Abstract translation: 公开了一种将具有n个二进制位的第一和第二符号编码为每个具有n-1个三进制数的第一和第二代码字的方法。 该方法涉及使用来自第一和第二符号中的每一个的预选位来确定包括n-1个字符串的至少两组代码字中的哪一组被用于编码。 还公开了一种类似的解码方法。 公开了用于执行编码和解码的装置。

公开(公告)号：US5734341A

公开(公告)日：1998-03-31

申请号：US743417

申请日：1996-11-01

Applicant: Christopher Paul Hulme Walker

Inventor： Christopher Paul Hulme Walker

IPC: H03M7/14 ,  H03M13/00 ,  H04B10/00 ,  H04J3/06 ,  H04L1/00 ,  H04L1/24 ,  H04L7/04 ,  H04L25/49 ,  H03M7/00

CPC classification number: H04L1/0057 ,  H04J3/0605 ,  H04J3/0632 ,  H04L1/0083 ,  H04L1/246 ,  H04L25/4908 ,  H04L7/046

Abstract: An encoding scheme relies on a d.c. balanced code wherein each message to be transmitted is sent as a plurality of symbols, each symbol having six bits, three ones and three zeros. Out of the twenty combinations of balanced six-bit codes, two codes are reserved to operate as control tokens, being 010101 and 101010. Because of the particular format of the symbols, control tokens can be easily detected. Furthermore, they can be combined in longer bit sequences for use as initialization and disconnect sequences.

Abstract translation: 编码方案依赖于直流 平衡代码，其中要发送的每个消息被发送为多个符号，每个符号具有六位，三位和三位零。 在平衡六位代码的二十种组合中，保留了两个代码作为控制令牌来操作，即010101和101010.由于符号的特定格式，可以方便地检测到控制令牌。 此外，它们可以以更长的比特序列组合用作初始化和断开序列。

公开(公告)号：US5731714A

公开(公告)日：1998-03-24

申请号：US535876

申请日：1995-09-28

Applicant: Trevor Monk ,  Curtis Dicke

Inventor： Trevor Monk ,  Curtis Dicke

IPC: H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  H03K17/165

Abstract: An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Abstract translation: 片外驱动电路可以在输出模式下工作，以将其输入端提供的信号驱动到输出端。 它也可以在信号通过输出端从外部电路驱动到芯片上的输入模式下工作。 在输出模式中，输出端子被钳位以减小过冲电压的影响，例如作为来自外部电路的反射的结果。

公开(公告)号：US5729157A

公开(公告)日：1998-03-17

申请号：US506879

申请日：1995-07-25

Applicant: Trevor Monk ,  Curtis Dicke

Inventor： Trevor Monk ,  Curtis Dicke

IPC: H03K19/003 ,  H03K19/0175 ,  H03K19/094 ,  H03K19/0948

CPC classification number: H03K19/00315 ,  H03K19/09429 ,  H03K19/09485

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential. An auxiliary pass transistor has a control terminal and a controllable path connected between a reference terminal and the control terminal of the pull-up transistor. An auxiliary control transistor has a control terminal connected to receive the control potential, and a controllable path connected between the output terminal and the control terminal of the auxiliary pass transistor. Auxiliary circuitry holds the control terminal of the auxiliary pass transistor in a state determined by the auxiliary control transistor. The auxiliary circuitry may include an auxiliary pull-down transistor having a controllable path connected between the control terminal of the auxiliary pass transistor and a reference potential, and a control terminal connected to a voltage selected to maintain the auxiliary pull-down transistor on.

Abstract translation: 描述了片外驱动器电路，其具有用于在片外驱动器电路被禁用时提供高电压保护的电路。 用于提供高电压保护的电路利用最小数量的晶体管，因此最小化片外驱动电路所使用的芯片面积。 片外驱动电路具有输入端和输出端。 上拉晶体管具有连接在第一电源电压和片外驱动电路的输出端之间的可控路径，以及连接到输入端的控制端，该通路被连接以将输入端与高电压隔离 应用于输出端子。 控制晶体管具有连接在上拉晶体管的控制端和输出端之间的可控路径，以及连接到控制电位的控制端。 辅助通过晶体管具有连接在参考端和上拉晶体管的控制端之间的控制端和可控路径。 辅助控制晶体管具有连接以接收控制电位的控制端子和连接在辅助传输晶体管的输出端子和控制端子之间的可控路径。 辅助电路将辅助通过晶体管的控制端子保持在由辅助控制晶体管确定的状态。 辅助电路可以包括辅助下拉晶体管，其具有连接在辅助传输晶体管的控制端子和参考电位之间的可控路径，以及连接到选择用于维持辅助下拉晶体管导通的电压的控制端子。