公开(公告)号：US11049968B2

公开(公告)日：2021-06-29

申请号：US15914202

申请日：2018-03-07

申请人： X-FAB SEMICONDUCTOR FOUNDRIES AG

发明人： Eng Gek Hee ,  Ek Chien Yeo ,  Steffen Thiem ,  Choon Swee Tan

IPC分类号： H01L29/78 ,  H01L29/792 ,  H01L29/66 ,  H01L29/786 ,  H01L29/788 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12

摘要： A semiconductor memory device comprising a strained semiconductor layer and a contact etch stop layer, CESL, wherein the strained semiconductor layer and the CESL are both arranged to reduce the probability of an electron tunnelling out of a charge trapping layer of the semiconductor memory device.

公开(公告)号：US10297502B2

公开(公告)日：2019-05-21

申请号：US15445728

申请日：2017-02-28

申请人： X-Celeprint Limited ,  X-FAB Semiconductor Foundries AG

发明人： Christopher Andrew Bower ,  Ronald S. Cok ,  William Andrew Nevin ,  Gabriel Kittler

IPC分类号： H01L25/00 ,  H01L21/78 ,  H01L21/762 ,  H01L21/683 ,  H01L21/84

摘要： A semiconductor structure suitable for micro-transfer printing includes a semiconductor substrate and a patterned insulation layer disposed on or over the semiconductor substrate. The insulation layer pattern forms one or more etch vias in contact with the semiconductor substrate. Each etch via is exposed. A semiconductor device is disposed on the patterned insulation layer and is surrounded by an isolation material in one or more isolation vias that are adjacent to the etch via. The etch via can be at least partially filled with a semiconductor material that is etchable with a common etchant as the semiconductor substrate. Alternatively, the etch via is empty and the semiconductor substrate is patterned to form a gap that separates at least a part of the semiconductor device from the semiconductor substrate and forms a tether physically connecting the semiconductor device to an anchor portion of the semiconductor substrate or the patterned insulation layer.

公开(公告)号：US10026734B2

公开(公告)日：2018-07-17

申请号：US14358067

申请日：2011-11-15

申请人： Brendan Toner ,  Tsui Ping Chu ,  Foo Sen Liew

发明人： Brendan Toner ,  Tsui Ping Chu ,  Foo Sen Liew

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L27/02 ,  H03F1/32 ,  H01L21/02 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51

摘要： A MOS device assembly having at least two transistors, each transistor having a gate region. The dimensions of the gate region of the first transistor are different from the dimensions of the gate region of the second transistor. The transconductance of the MOS device assembly is substantially uniform when the gate regions of the first and second transistors are biased using the same voltage.

公开(公告)号：US09793338B2

公开(公告)日：2017-10-17

申请号：US13810398

申请日：2010-07-16

申请人： Tsui Ping Chu ,  Peng Yang ,  Evie Siaw Hei Kho ,  Yong Kheng Ang ,  Swee Hua Tia

发明人： Tsui Ping Chu ,  Peng Yang ,  Evie Siaw Hei Kho ,  Yong Kheng Ang ,  Swee Hua Tia

IPC分类号： H01L29/49 ,  H01L49/02 ,  H01G7/06 ,  H01L27/08

CPC分类号： H01L28/60 ,  H01G7/06 ,  H01L27/0802 ,  H01L28/40

摘要： A semiconductor device comprising a semiconductor substrate and a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises a capacitor stack comprising a lower and an upper capacitor, respectively comprising first and second dielectric materials, wherein the first and second dielectric materials are different materials and/or have different thicknesses from each other. This can minimize the voltage dependence of the capacitance of the composite capacitor structure. It is also possible to provide a composite capacitor structure on the semiconductor substrate, wherein the composite capacitor structure comprises at least a first and a second capacitor stack, each comprising a lower and an upper capacitor. The capacitors can be MIM capacitors.

公开(公告)号：US09748383B2

公开(公告)日：2017-08-29

申请号：US12867257

申请日：2009-02-12

申请人： Elizabeth Ching Tee Kho ,  Zheng Chao Liu ,  Deb Kumar Pal ,  Michael Mee Gouh Tiong ,  Jian Liu ,  Kia Yaw Kee

发明人： Yong Hai Hu ,  Elizabeth Ching Tee Kho ,  Zheng Chao Liu ,  Deb Kumar Pal ,  Michael Mee Gouh Tiong ,  Jian Liu ,  Kia Yaw Kee ,  William Lau

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/7834 ,  H01L29/0653 ,  H01L29/42368 ,  H01L29/7835

摘要： A Metal Oxide Semiconductor (MOS) transistor comprising: a source; a gate; and a drain, the source, gate and drain being located in or on a well structure of a first doping polarity located in or on a substrate; wherein at least one of the source and the drain comprises a first structure comprising: a first region forming a first drift region, the first region being of a second doping polarity opposite the first doping polarity; a second region of the second doping polarity in or on the first region, the second region being a well region and having a doping concentration which is higher than the doping concentration of the first region; and a third region of the second doping polarity in or on the second region. Due to the presence of the second region the transistor may have a lower ON resistance when compared with a similar transistor which does not have the second region. The breakdown voltage may be influenced only to a small extent.

公开(公告)号：US09559170B2

公开(公告)日：2017-01-31

申请号：US13410016

申请日：2012-03-01

申请人： Paul Ronald Stribley

发明人： Paul Ronald Stribley

IPC分类号： H01L29/10 ,  H01L27/02 ,  H01L29/78 ,  H01L29/861 ,  H01L29/06 ,  H01L29/423

CPC分类号： H01L29/00 ,  H01L27/027 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/7835 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection including a source, a gate, a drain having a drain diffusion, and a diffusion region extending from, or located under, the drain diffusion. The source, the gate, the drain and the diffusion region are located in or on a substrate. The diffusion region is laterally spaced from at least one of the gate or the outer edge of the drain diffusion.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件，包括源极，栅极，具有漏极扩散的漏极，以及从漏极扩散区延伸或位于其下方的扩散区域。 源极，栅极，漏极和扩散区域位于衬底中或衬底上。 扩散区域与漏极扩散器的栅极或外部边缘中的至少一个侧向间隔开。

公开(公告)号：US09524963B2

公开(公告)日：2016-12-20

申请号：US13833684

申请日：2013-03-15

申请人： X-FAB Semiconductor Foundries AG

发明人： Paul Ronald Stribley

IPC分类号： H01L23/52 ,  H01L27/08 ,  H01L29/24 ,  H01L49/02

CPC分类号： H01L27/0805 ,  H01L28/60

摘要： A semiconductor device comprising: a first, a second and a third conductive layer; the second conductive layer being located between the first and third conductive layers; wherein respective regions of the first and second conductive layers form a first capacitor; and respective regions of the second and third conductive layers form a second capacitor.

公开(公告)号：US09304104B2

公开(公告)日：2016-04-05

申请号：US14072908

申请日：2013-11-06

申请人： X-FAB Semiconductor Foundries AG

发明人： Sang Sool Koo ,  Ling Gang Fang

IPC分类号： G01N27/414

CPC分类号： G01N27/4148

摘要： A CMOS or bipolar based Ion Sensitive Field Effect Transistor (ISFET) comprising an ion sensitive recess for holding a liquid wherein the recess is formed at least partly on top of a gate of the transistor. There is also provided a method of manufacturing an I on Sensitive Field Effect Transistor (ISFET) utilizing CMOS processing steps, the method comprising forming an ion sensitive recess for holding a liquid at least partly on top of a gate of the transistor.

摘要翻译： 一种CMOS或双极型离子敏感场效应晶体管（ISFET），其包括用于保持液体的离子敏感凹槽，其中凹部至少部分地形成在晶体管的栅极的顶部。 还提供了利用CMOS处理步骤制造I敏感场效应晶体管（ISFET）的方法，所述方法包括形成用于至少部分地保持液晶的离子敏感凹槽至晶体管的栅极的顶部。

公开(公告)号：US09059110B2

公开(公告)日：2015-06-16

申请号：US13394238

申请日：2009-09-04

申请人： Hyung Sun Yook ,  Tsui Ping Chu ,  Poh Ching Sim

发明人： Hyung Sun Yook ,  Tsui Ping Chu ,  Poh Ching Sim

IPC分类号： H01L23/52 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L23/3178 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/85013 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/00

摘要： A method of reducing contamination of contact pads in a metallization system of a semiconductor device. Fluorine contamination of contact pads in a semiconductor device can be reduced by appropriately covering the sidewall portions of a metallization system in the scribe lane in order to significantly reduce or suppress the out diffusion of fluorine species, which may react with the exposed surface areas of the contact pads. The quality of the bond contacts is enhanced, possibly without requiring any modifications in terms of design rules and electrical specifications.

摘要翻译： 一种减少半导体器件的金属化系统中接触焊盘污染的方法。 可以通过适当地覆盖划线中的金属化系统的侧壁部分来减少半导体器件中的接触焊盘的氟污染，以便显着地减少或抑制氟物质的扩散，这可能与暴露的表面区域 接触垫 增强了触点接触的质量，可能不需要对设计规则和电气规格进行任何修改。

公开(公告)号：US20150108559A1

公开(公告)日：2015-04-23

申请号：US14390431

申请日：2012-04-05

申请人： Eng Gek Hee ,  Ka Siong Wisley Ung

发明人： Eng Gek Hee ,  Ka Siong Wisley Ung

IPC分类号： H01L21/28 ,  H01L29/788 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L21/28273 ,  H01L27/11517 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

摘要： A method of fabricating a tunnel oxide layer for a semiconductor memory device, the method comprising: fabricating on a substrate a first oxide layer by an in-situ-steam-generation process; and fabricating at least one further oxide layer by a furnace oxidation process, wherein during fabrication of the at least one further oxide layer, reactive gases penetrate the first oxide layer and react with the silicon substrate to form at least a first portion of the at least one further oxide layer beneath the first oxide layer.

摘要翻译： 一种制造用于半导体存储器件的隧道氧化物层的方法，所述方法包括：通过原位蒸汽生成工艺在衬底上制造第一氧化物层; 以及通过炉氧化工艺制造至少一个另外的氧化物层，其中在制造所述至少一个另外的氧化物层期间，反应性气体穿透所述第一氧化物层并与所述硅衬底反应以形成所述至少一个至少一个的第一部分 在第一氧化物层下面的另一个氧化物层。