利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

30 条记录 (耗时 0.022 秒)

    Semiconductor integrated circuit
    5.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06677797B2

    公开(公告)日：2004-01-13

    申请号：US10023947

    申请日：2001-12-21

    申请人： Atsushi Kameyama ,  Tsuneaki Fuse ,  Masako Yoshida ,  Kazunori Ohuchi

    发明人： Atsushi Kameyama ,  Tsuneaki Fuse ,  Masako Yoshida ,  Kazunori Ohuchi

    IPC分类号： H03L500

    CPC分类号： H03K19/0016

    摘要： An integrated circuit has first and second logic circuits having common input terminals and the same complementary logic function. The first logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a high threshold value, while the second logic circuit has a p-type FET circuit block and an n-type FET circuit block each with a low threshold value. An output switch circuit intervenes between the p-type FET and n-type FET circuit blocks in each logic circuit and controls the power supply connection to each logic circuit. In operation, the output of the second logic circuit is connected to the output terminal to realize a low power consumption. In the standby state, the output of the first logic circuit is connected to the output terminal to realize a low leakage current.

    摘要翻译： 集成电路具有第一和第二逻辑电路，其具有公共的输入端和相同的互补逻辑功能。 第一逻辑电路具有每个具有高阈值的p型FET电路块和n型FET电路块，而第二逻辑电路具有p型FET电路块和n型FET电路块，每个具有 低阈值。 输出开关电路插入每个逻辑电路中的p型FET和n型FET电路块之间，并且控制到每个逻辑电路的电源连接。 在操作中，第二逻辑电路的输出连接到输出端以实现低功耗。 在待机状态下，第一逻辑电路的输出连接到输出端子以实现低泄漏电流。

    Semiconductor integrated circuit
    6.
    发明授权
    Semiconductor integrated circuit 失效
    半导体集成电路

    公开(公告)号：US06455901B2

    公开(公告)日：2002-09-24

    申请号：US09803944

    申请日：2001-03-13

    申请人： Atsushi Kameyama ,  Tsuneaki Fuse ,  Masako Yoshida

    发明人： Atsushi Kameyama ,  Tsuneaki Fuse ,  Masako Yoshida

    IPC分类号： H01L31062

    CPC分类号： H03K19/00384 ,  H01L27/092 ,  H03K19/0013

    摘要： A semiconductor integrated circuit has a logic circuit operated at a small power supply voltage of about 0.5V, wherein a noise margin of the logic circuit can be set at a larger value even if characteristics of the circuit vary depending upon manufacturing process conditions. Satisfactory speed can be ensured during an operation and power consumption can be reduced during a stand-by time. This is attained by controlling individual potentials of first and second conductivity type wells in which a logic circuit is formed. For this purpose, two voltage supply circuits for controlling voltages of the wells and a logic threshold voltage generator are provided.

    摘要翻译： 半导体集成电路具有在约0.5V的小电源电压下工作的逻辑电路，其中即使电路的特性根据制造工艺条件而变化，逻辑电路的噪声容限也可以被设置为更大的值。 在操作期间可以确保令人满意的速度，并且可以在待机时间内降低功耗。 这是通过控制其中形成逻辑电路的第一和第二导电类型阱的各个电位来实现的。 为此，提供了用于控制阱的电压的两个电压供应电路和逻辑阈值电压发生器。

    Standard-cell type semiconductor logic LSI with logical amplitude enhancer
    8.
    发明授权
    Standard-cell type semiconductor logic LSI with logical amplitude enhancer 失效
    具有逻辑振幅增强器的标准电池型半导体逻辑LSI

    公开(公告)号：US5225718A

    公开(公告)日：1993-07-06

    申请号：US529441

    申请日：1990-05-29

    申请人： Toshiki Seshita ,  Atsushi Kameyama ,  Katsue Kawakyu ,  Tadahiro Sasaki

    发明人： Toshiki Seshita ,  Atsushi Kameyama ,  Katsue Kawakyu ,  Tadahiro Sasaki

    IPC分类号： H01L27/02 ,  H03K3/037 ,  H03K19/0185 ,  H03K19/0952 ,  H03K19/173

    CPC分类号： H03K19/018535 ,  H03K19/0952 ,  H03K19/1735 ,  H03K3/037 ,  H01L27/0207

    摘要： A standard cell type gallium arsenide logic integrated circuit device includes arrays of standard cells connected to each other on a chip substrate. Each of the standard cells includes a plurality of gallium arsenide logic gates of previously selected type such as NOR gates and an inverter. The logic gate has a direct-coupled type FET logic circuit structure. In each of the standard cells, level-shift circuits are provided only for inputs of those logic gates which are directly connected to connection terminals directly associated with the other standard cell. The level-shift circuits enhance the swing width of a logic signal transmitted between the standard cells which are associated with one another, thereby increasing the operation margin. Such a level-shift circuit is not provided for internal interconnection wirings between the logic gates inside the standard cell.

    摘要翻译： 标准单元型砷化镓逻辑集成电路器件包括在芯片衬底上彼此连接的标准单元阵列。 每个标准单元包括多个先前选择类型的砷化镓逻辑门，例如NOR门和反相器。 逻辑门具有直接耦合型FET逻辑电路结构。 在每个标准单元中，仅为直接连接到与另一个标准单元相关联的连接端子的那些逻辑门的输入端提供电平移位电路。 电平移位电路增强了在彼此相关联的标准单元之间传输的逻辑信号的摆幅，从而增加了操作余量。 这种电平移位电路不提供在标准单元内的逻辑门之间的内部互连布线。

    Unsaturated carboxylic ester compound, process for producing the same, and composition curable with actinic energy ray
    10.
    发明授权
    Unsaturated carboxylic ester compound, process for producing the same, and composition curable with actinic energy ray 有权
    不饱和羧酸酯化合物，其制备方法和可用光化能光线固化的组合物

    公开(公告)号：US07057063B2

    公开(公告)日：2006-06-06

    申请号：US10202092

    申请日：2002-07-25

    申请人： Tadatomi Nishikubo ,  Atsushi Kameyama ,  Masaki Sasaki ,  Masatoshi Kusama

    发明人： Tadatomi Nishikubo ,  Atsushi Kameyama ,  Masaki Sasaki ,  Masatoshi Kusama

    IPC分类号： C07C69/76

    CPC分类号： C08F20/26 ,  C07C69/533 ,  C07C69/54 ,  C08F20/28

    摘要： An unsaturated monocarboxylic ester compound has at least two structures represented by the following general formula (1): wherein R1 represents a hydrogen atom or an alkyl group of 1 to 6 carbon atoms, and R2, R3 and R4 independently represent a hydrogen atom, an alkyl group of 1 to 6 carbon atoms, an aryl group, an aralkyl group, a cyano group, a fluorine atom, or a furyl group. A curable composition comprises (A) the unsaturated carboxylic ester compound having two or more structures represented by the general formula (1) mentioned above, (B) a polymerization initiator, and optionally (C) a diluent.

    摘要翻译： 不饱和单羧酸酯化合物具有由以下通式（1）表示的至少两种结构：其中R 1表示氢原子或1至6个碳原子的烷基，R“ 2，R 3和R 4独立地表示氢原子，1至6个碳原子的烷基，芳基，芳烷基， 氰基，氟原子或呋喃基。 可固化组合物包含（A）具有两个或更多个由上述通式（1）表示的结构的不饱和羧酸酯化合物，（B）聚合引发剂和任选的（C）稀释剂。