公开(公告)号：US20120106259A1

公开(公告)日：2012-05-03

申请号：US12915310

申请日：2010-10-29

申请人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ping Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C16/06 ,  G11C16/04

CPC分类号： G11C16/3454 ,  G11C16/0483 ,  G11C16/10

摘要： A method includes performing a first programming operation on a plurality of memory cells in a same programming cycle; and performing a verification operation on the plurality of memory cells to find failed memory cells in the plurality of memory cells, wherein the failed memory cells are not successfully programmed in the first programming operation; and performing a second programming operation on the failed memory cells. Passed memory cells successfully programmed in the first programming operation are not programmed in the second programming operation.

摘要翻译： 一种方法包括在相同的编程周期中对多个存储单元执行第一编程操作; 以及对所述多个存储单元执行验证操作以在所述多个存储器单元中找到故障存储器单元，其中在所述第一编程操作中所述故障存储单元未成功编程; 以及对所述故障存储器单元执行第二编程操作。 在第二个编程操作中，没有编程在第一个编程操作中成功编程的通过的存储单元。

公开(公告)号：US20100053965A1

公开(公告)日：2010-03-04

申请号：US12511927

申请日：2009-07-29

申请人： CHING-KUN CHANG ,  CHENG-HSIUNG KUO ,  YEN-FU LIU

发明人： CHING-KUN CHANG ,  CHENG-HSIUNG KUO ,  YEN-FU LIU

IPC分类号： F21S4/00

CPC分类号： F21V15/015 ,  F21K9/66 ,  F21S4/28 ,  F21V31/03 ,  F21Y2103/10 ,  F21Y2115/10

摘要： A LED lamp comprises: a lamp base; an illuminating component, mounted on the lamp base, wherein the illuminating component comprises a circuit board and a plurality of LEDs arranged on the circuit board; a lamp shade, mounted on the lamp shade for enclosing the illuminating element, wherein the lamp shade has at least one open area; and at least one waterproof and ventilative element, disposed on the open area for covering the open area; thereby, vapors inside the lamp shade can vacate out of the LED lamp through the waterproof and ventilative element, while external vapors cannot infiltrate into the lamp shade through the waterproof and ventilative element.

摘要翻译： 一种LED灯包括：灯座; 安装在灯座上的照明部件，其中所述照明部件包括布置在所述电路板上的电路板和多个LED; 灯罩，安装在灯罩上以封闭照明元件，其中灯罩具有至少一个开放区域; 和至少一个防水和通风元件，设置在开放区域上以覆盖开放区域; 因此，灯罩内部的蒸气可以通过防水和通风元件从LED灯中腾出，而外部蒸气不能通过防水和通风元件渗透到灯罩中。

公开(公告)号：US07282410B2

公开(公告)日：2007-10-16

申请号：US10895881

申请日：2004-07-21

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Chin-Huang Wang

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  H01L27/115 ,  H01L27/11521

摘要： A method of embedding the forming of peripheral devices such as HV-LDMOS into the forming of flash memory is presented. A layered structure is formed with a first insulating layer formed on a substrate, and a poly silicon formed on the first insulating layer in the flash memory region. A mask layer is formed. Openings are formed in the flash memory region in the peripheral region. A local oxidation of silicon (LOCOS) is performed to form thick oxides on poly silicon, and a field oxide on silicon substrate respectively. The mask layer is removed. A control gate and a control gate oxide are formed on the thick oxide and the poly silicon. A gate electrode is formed with at least one end residing on a field oxide so that the resulting HV-LDMOS has a high breakdown voltage. Spacers and a source/drain of the flash cells and HV-LDMOSs are then formed.

摘要翻译： 提出了一种将诸如HV-LDMOS之类的外围设备的形成嵌入到闪速存储器的形成中的方法。 层叠结构形成有在基板上形成的第一绝缘层，以及形成在闪存区域中的第一绝缘层上的多晶硅。 形成掩模层。 开口形成在周边区域的闪存区域中。 进行硅的局部氧化（LOCOS）以在多晶硅上形成厚氧化物，分别在硅衬底上形成场氧化物。 去除掩模层。 在厚氧化物和多晶硅上形成控制栅极和控制栅极氧化物。 栅电极形成有驻留在场氧化物上的至少一端，使得所得的HV-LDMOS具有高的击穿电压。 然后形成闪存单元和HV-LDMOS的间隔物和源极/漏极。

公开(公告)号：US20070155092A1

公开(公告)日：2007-07-05

申请号：US11319357

申请日：2005-12-29

申请人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

发明人： Hsiang-Tai Lu ,  Cheng-Hsiung Kuo ,  Yue-Der Chih

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7881 ,  H01J9/025 ,  H01L27/0207 ,  H01L29/40114

摘要： A method for forming a tip is disclosed. A layer is formed overlying a substrate. A mask layer is formed overlying the layer. The mask is patterned to form a mask pattern comprising an inner portion and an outer portion, wherein the inner portion is surrounded by the outer portion. The layer uncovered by the mask pattern is treated to form a reaction mask, wherein at least one portion of the reaction mask connect to form a tip of the layer under the inner portion of the mask pattern.

摘要翻译： 公开了一种用于形成尖端的方法。 层叠在衬底上方。 形成覆盖层的掩模层。 将掩模图案化以形成包括内部部分和外部部分的掩模图案，其中内部部分被外部部分包围。 处理由掩模图案覆盖的层以形成反应掩模，其中反应掩模的至少一部分连接以在掩模图案的内部部分的下方形成该顶层。

公开(公告)号：US07002861B2

公开(公告)日：2006-02-21

申请号：US10826457

申请日：2004-04-16

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： G11C7/00

CPC分类号： G11C16/32 ,  G11C7/22 ,  G11C8/08

摘要： An improved memory device and the method for programming the same are disclosed. The memory device includes at least one memory block requiring a word line pre-charge time to be long enough to program one or more selected memory cells. A monitoring circuit is added for detecting one or more word lines to reach a predetermined threshold voltage to enable a predetermined high voltage to be supplied to one or more latches of the memory cells.

摘要翻译： 公开了一种改进的存储器件及其编程方法。 存储器件包括至少一个需要字线预充电时间足以对一个或多个所选择的存储器单元进行编程的存储器块。 添加监视电路，用于检测一个或多个字线以达到预定的阈值电压，以使预定的高电压能够提供给存储器单元的一个或多个锁存器。

公开(公告)号：US20050265085A1

公开(公告)日：2005-12-01

申请号：US10854819

申请日：2004-05-27

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/24

CPC分类号： G11C16/24 ,  G11C16/10

摘要： A source line driver is provided. The source line driver for a flash memory includes a plurality of source driving units and a control circuit to drive a plurality of source lines. Each source line is coupled to memory cells in a row. Each source driving unit drives the corresponding source line and is coupled to the control circuit at a common node. The control circuit is coupled between the common node and a ground line. When any memory cell is assigned to execute a program operation, the control circuit isolates the common node and the ground. When the memory cells are not assigned to execute the program operation, the control circuit couples the common node to the ground line.

摘要翻译： 提供源线驱动程序。 用于闪速存储器的源极线驱动器包括多个源极驱动单元和用于驱动多个源极线的控制电路。 每个源极线被连接到一行中的存储器单元。 每个源驱动单元驱动相应的源极线并且在公共节点耦合到控制电路。 控制电路耦合在公共节点和地线之间。 当分配任何存储单元以执行编程操作时，控制电路将公共节点和地线隔离。 当不分配存储单元来执行编程操作时，控制电路将公共节点耦合到接地线。

公开(公告)号：US20050259470A1

公开(公告)日：2005-11-24

申请号：US11026910

申请日：2004-12-30

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： G11C7/14 ,  G11C7/20 ,  G11C11/24 ,  G11C11/34 ,  G11C16/06 ,  G11C16/28 ,  G11C16/30

CPC分类号： G11C16/28 ,  G11C7/14 ,  G11C7/20 ,  G11C16/30

摘要： A reference voltage generator circuit for nonvolatile memory devices is disclosed. The circuit has at least one sense amplifier bias reference voltage generator (SABRVG) for generating a reference voltage at a predetermined reference point that is coupled to a start-up bias reference voltage generator (SBRVG). It also includes a monitor reference voltage generator (MRVG) for generating a monitor reference voltage, and a comparison module for comparing the monitor reference voltage with the reference voltage to produce a start-up control signal, wherein the SBRVG enhances a changing speed of the reference voltage during a reading cycle of the nonvolatile memory and when the monitor reference and the reference voltages are matched, the start-up control signal stops the SBRVG from operating, thereby having the SABRVG maintain the reference voltage.

公开(公告)号：US20050254331A1

公开(公告)日：2005-11-17

申请号：US10847106

申请日：2004-05-17

申请人： Cheng-Hsiung Kuo

发明人： Cheng-Hsiung Kuo

IPC分类号： G11C8/10 ,  G11C11/34 ,  G11C16/08

CPC分类号： G11C8/10 ,  G11C16/08

摘要： A wordline decoder for a memory device drives a word line of a memory array and comprises a first circuit, a second circuit, and a buffer circuit. The first circuit receives voltage from a first voltage source. The second circuit receives voltage from a second voltage source. During an erase cycle, the buffer circuit receives a third voltage higher than the second voltage and lower than the first voltage. During read and program cycles, the buffer circuit receives a fourth voltage substantially equal to the first and second voltage.

摘要翻译： 用于存储器件的字线解码器驱动存储器阵列的字线，并且包括第一电路，第二电路和缓冲电路。 第一电路从第一电压源接收电压。 第二电路从第二电压源接收电压。 在擦除周期期间，缓冲电路接收高于第二电压并低于第一电压的第三电压。 在读取和编程周期期间，缓冲电路接收基本上等于第一和第二电压的第四电压。

公开(公告)号：US20050132315A1

公开(公告)日：2005-06-16

申请号：US11044750

申请日：2005-01-26

申请人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

发明人： Hsiao-Hui Chen ,  Cheng-Hsiung Kuo

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5077

摘要： Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring location within which may be formed at least one optional wiring pattern. When there is designed within an unoccupied equivalent wiring location for a single wiring layout record within the series of wiring layout records at least one optional wiring pattern and an interconnect option to the at least one optional wiring pattern.

摘要翻译： 在修改图案化导体层的方法和用于修改图案化导体层的系统中，在针对一系列微电子制造的布线布局数据库内的一系列布线布局记录内的每个布线布局记录内提供未占用的等效布线 其中的位置可以形成至少一个可选的布线图案。 当在一系列布线布局内的单个布线布局记录的未占用的等效布线位置内设计有至少一个可选布线图案和至少一个可选布线图案的互连选项时。

公开(公告)号：US06842381B2

公开(公告)日：2005-01-11

申请号：US10725809

申请日：2003-12-02

申请人： Yue-Der Chih ,  Ching-Huang Wang ,  Cheng-Hsiung Kuo

发明人： Yue-Der Chih ,  Ching-Huang Wang ,  Cheng-Hsiung Kuo

IPC分类号： G11C8/02 ,  G11C16/04 ,  G11C16/30 ,  G11C29/50

CPC分类号： G11C29/12005 ,  G11C16/04 ,  G11C16/30 ,  G11C29/50

摘要： Voltage-dropping components are bypassed during testing of the erasing of a flash memory device thereby effectively lowering the applied erase voltage to the marginal level desired (VME). These voltage-dropping components may be a plurality of diode-connected NMOS transistors. If a plurality of diode-connected NMOS transistors are used, the voltage applied to the flash macro is reduced by m*Vt, where m is the number of bypassed diode connected NMOS transistors and Vt is the threshold voltage of the NMOS transistors. In normal operation, the voltage dropping components are placed in series with the charge pump, thereby returning the voltage applied to the flash macro to the normal level (VNE).

摘要翻译： 在测试闪速存储器件的擦除期间旁路掉电元件，从而有效地将所施加的擦除电压降低到期望的边际电平（VME）。 这些降压组件可以是多个二极管连接的NMOS晶体管。 如果使用多个二极管连接的NMOS晶体管，则施加到闪存宏的电压减小m * Vt，其中m是旁路二极管连接的NMOS晶体管的数量，Vt是NMOS晶体管的阈值电压。 在正常操作中，降压元件与电荷泵串联放置，从而将施加到闪光灯的电压返回到正常电平（VNE）。