公开(公告)号：US08633588B2

公开(公告)日：2014-01-21

申请号：US13332658

申请日：2011-12-21

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/48

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 焊料电阻层设置在衬底上，具有覆盖第一导电迹线的一部分的延伸部分，其中阻焊层的延伸部分的宽度大于第一导电迹线部分的宽度。 半导体管芯设置在第一导电迹线上。

公开(公告)号：US08502377B2

公开(公告)日：2013-08-06

申请号：US13110935

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example.

Abstract translation: 1.一种封装基板，包括设置在所述封装基板的芯片附着面上的导电图案; 至少一个凸起轨迹嵌入到导电图案中; 以及与导电图案中的凸起轨迹一起布置的至少一个间隙，以将凸起迹线与导电图案的主体部分分离。 凸起迹线可以具有从平面图和宽度基本上在10um到40um之间的宽度，并且具有基本上在70μm和130μm之间的长度。

公开(公告)号：US20130161810A1

公开(公告)日：2013-06-27

申请号：US13332658

申请日：2011-12-21

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/498

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 焊料电阻层设置在衬底上，具有覆盖第一导电迹线的一部分的延伸部分，其中阻焊层的延伸部分的宽度大于第一导电迹线部分的宽度。 半导体管芯设置在第一导电迹线上。

公开(公告)号：US20120126368A1

公开(公告)日：2012-05-24

申请号：US13109740

申请日：2011-05-17

Applicant: Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L29/02 ,  H01L23/488

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一钝化层设置在基板上。 凸块下金属层设置在第一钝化层上。 无源器件设置在凸块下金属层上

公开(公告)号：US08987897B2

公开(公告)日：2015-03-24

申请号：US13109740

申请日：2011-05-17

Applicant: Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01Q23/00 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一钝化层设置在基板上。 凸块下金属层设置在第一钝化层上。 无源器件设置在凸块下金属层上。

公开(公告)号：US20120032343A1

公开(公告)日：2012-02-09

申请号：US13110935

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example.

Abstract translation: 1.一种封装基板，包括设置在所述封装基板的芯片附着面上的导电图案; 至少一个凸起轨迹嵌入到所述导电图案中; 以及与导电图案中的凸起轨迹一起布置的至少一个间隙，以将凸起迹线与导电图案的主体部分分离。 凸起迹线可以具有从平面图和宽度基本上在10μm至40μm之间的宽度，并且具有基本上在70μm和130μm之间的长度。