公开(公告)号：US20130221536A1

公开(公告)日：2013-08-29

申请号：US13612860

申请日：2012-09-13

Applicant: Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract translation: 倒装芯片封装包括耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱仅围绕所述通孔开口设置在所述捕获垫的一侧上。

公开(公告)号：US20120267779A1

公开(公告)日：2012-10-25

申请号：US13430439

申请日：2012-03-26

Applicant: Tzu-Hung LIN ,  Wen-Sung HSU ,  Tai-Yu CHEN

Inventor： Tzu-Hung LIN ,  Wen-Sung HSU ,  Tai-Yu CHEN

IPC: H01L23/498

CPC classification number: H01L24/14 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/04 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/02125 ,  H01L2224/02165 ,  H01L2224/02166 ,  H01L2224/02181 ,  H01L2224/0219 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/11462 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14515 ,  H01L2224/16238 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/07025 ,  H01L2924/18161 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a semiconductor die having a central area and a peripheral area surrounding the central area. A first conductive bump is disposed on the semiconductor die in the central area. A second conductive bump is disposed on the semiconductor die in the peripheral area. An area ratio of the first conductive bump to the second conductive bump from a top view is larger than 1, and less than or equal to 3.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括具有中心区域和围绕中心区域的周边区域的半导体管芯。 第一导电凸块设置在中心区域的半导体管芯上。 第二导电凸块设置在周边区域的半导体管芯上。 从顶视图看，第一导电凸块与第二导电凸块的面积比大于1，小于或等于3。

公开(公告)号：US09437512B2

公开(公告)日：2016-09-06

申请号：US13612764

申请日：2012-09-12

Applicant: Thomas Matthew Gregorich ,  Tzu-Hung Lin

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L23/31 ,  H01L25/10 ,  H01L23/498

CPC classification number: H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/0002 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00

Abstract: An integrated circuit (IC) package structure is provided, including: a first integrated circuit (IC) package, including: a first package substrate, having opposite first and second surfaces, wherein a first semiconductor chip is disposed over a first portion of the first surface of the first package substrate. In addition, a second integrated circuit (IC) package is disposed on a second portion different from the first portion of the first surface of the first package substrate, including: a second package substrate, having opposite third and fourth surfaces, wherein a second semiconductor chip is disposed over a portion of the third surface of the second package substrate, and the second semiconductor chip has a function different from that of the first semiconductor chip.

Abstract translation: 提供了一种集成电路（IC）封装结构，包括：第一集成电路（IC）封装，包括：具有相对的第一和第二表面的第一封装衬底，其中第一半导体芯片设置在第一 第一封装基板的表面。 此外，第二集成电路（IC）封装设置在与第一封装衬底的第一表面的第一部分不同的第二部分上，包括：具有相反的第三和第四表面的第二封装衬底，其中第二半导体 芯片设置在第二封装衬底的第三表面的一部分上，并且第二半导体芯片具有与第一半导体芯片的功能不同的功能。

公开(公告)号：US08987897B2

公开(公告)日：2015-03-24

申请号：US13109740

申请日：2011-05-17

Applicant: Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

Inventor： Kuei-Ti Chan ,  Tzu-Hung Lin ,  Ching-Liou Huang

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01Q23/00 ,  H01L23/525

CPC classification number: H01L23/528 ,  H01L23/3171 ,  H01L23/5227 ,  H01L23/525 ,  H01L23/645 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2223/6677 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13023 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/014 ,  H01L2924/12 ,  H01L2924/1206 ,  H01Q23/00 ,  H01L2224/05552

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first passivation layer is disposed on the substrate. An under bump metallurgy layer is disposed on the first passivation layer. A passive device is disposed on the under bump metallurgy layer.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一钝化层设置在基板上。 凸块下金属层设置在第一钝化层上。 无源器件设置在凸块下金属层上。

公开(公告)号：US20120032343A1

公开(公告)日：2012-02-09

申请号：US13110935

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/498 ,  H01L23/48

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example.

Abstract translation: 1.一种封装基板，包括设置在所述封装基板的芯片附着面上的导电图案; 至少一个凸起轨迹嵌入到所述导电图案中; 以及与导电图案中的凸起轨迹一起布置的至少一个间隙，以将凸起迹线与导电图案的主体部分分离。 凸起迹线可以具有从平面图和宽度基本上在10μm至40μm之间的宽度，并且具有基本上在70μm和130μm之间的长度。

公开(公告)号：US20170004288A1

公开(公告)日：2017-01-05

申请号：US15198427

申请日：2016-06-30

Applicant: Tzu-Hung LIN

Inventor： Tzu-Hung LIN ,  Kuang-Lung KO ,  Yi-Ning SU

IPC: G06F19/00 ,  G06T1/00 ,  H04L29/06 ,  G06K19/077

CPC classification number: G06F19/321 ,  G16H15/00 ,  H04L63/102

Abstract: The present invention is related to an interactive and multimedia medical report system and method thereof. The system comprises a test unit, a marking unit, a database, and an electronic device. The test unit enables generation of an image file, wherein a predefined tag is established in the first position and a special tag is established in the second position. The database is connected to the marking unit and stores the medical report comprising the predefined and special tags, and at least one of the tags established in the image file. The electronic device comprises a processing unit, which makes connections with the database through the communication unit for retrieval of the medical report. The electronic device further comprises a display unit, which is configured to show the predefined tag and the special tag, and at least one of the tags of the image file. The present disclosure further provides an interactive multimedia method for medical report.

Abstract translation: 本发明涉及一种交互式多媒体医疗报告系统及其方法。 该系统包括测试单元，标记单元，数据库和电子设备。 测试单元能够生成图像文件，其中在第一位置建立预定义的标签，并且在第二位置中建立特殊标签。 数据库连接到标记单元并存储包括预定义和特殊标签的医疗报告以及在图像文件中建立的至少一个标签。 电子设备包括处理单元，其通过通信单元与数据库建立连接，用于检索医疗报告。 电子设备还包括显示单元，其被配置为显示预定标签和特殊标签，以及图像文件的至少一个标签。 本公开还提供了用于医疗报告的交互式多媒体方法。

公开(公告)号：US09064757B2

公开(公告)日：2015-06-23

申请号：US13612860

申请日：2012-09-13

Applicant: Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

Inventor： Thomas Matthew Gregorich ,  Tzu-Hung Lin ,  Che-Ya Chou

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0554 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00015 ,  H01L2924/00012 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05552

Abstract: A flip chip package includes a carrier coupled to a die. The carrier includes: at least a via, for coupling the surface of the carrier to electrical traces in the carrier; and at least a capture pad electrically coupled to the via, wherein the capture pad is plated over the via. The die includes: at least a bond pad formed on the surface of the die; and at least a copper column, formed on the bond pad for coupling the die to the capture pad on the carrier, wherein the copper column is disposed on one side of the capture pad about the via opening only.

Abstract translation: 倒装芯片封装包括耦合到管芯的载体。 载体包括：用于将载体的表面耦合到载体中的电迹线的至少一个通孔; 以及至少一个电耦合到所述通孔的捕获垫，其中所述捕获垫被电镀在所述通孔上。 模具包括：至少形成在模具表面上的接合焊盘; 以及形成在所述接合焊盘上的至少一个铜柱，用于将所述管芯耦合到所述载体上的捕获垫，其中所述铜柱仅围绕所述通孔开口设置在所述捕获垫的一侧上。

公开(公告)号：US08957518B2

公开(公告)日：2015-02-17

申请号：US13616890

申请日：2012-09-14

Applicant: Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

Inventor： Thomas Matthew Gregorich ,  Andrew C. Chang ,  Tzu-Hung Lin

IPC: H01L23/48 ,  H01L21/00 ,  H01L23/495

CPC classification number: H01L24/81 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

Abstract: The invention provides a molded interposer package and a method for fabricating the same. The molded interposer package includes a plurality of metal studs. A molding material encapsulates the metal studs leaving the bottom surfaces of the metal studs exposed. A first chip is disposed on the molding material, connecting to the top surfaces of the metal studs. A plurality of solder balls connects and contacts to the bottom surfaces of the metal studs.

Abstract translation: 本发明提供一种模制插入器封装及其制造方法。 模制插入器封装包括多个金属螺柱。 模制材料封装离开暴露的金属螺柱的底表面的金属螺柱。 第一芯片设置在模制材料上，连接到金属螺柱的顶表面。 多个焊球连接并接触到金属螺柱的底表面。

公开(公告)号：US08633588B2

公开(公告)日：2014-01-21

申请号：US13332658

申请日：2011-12-21

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/48

CPC classification number: H01L24/29 ,  H01L21/563 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/26175 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

Abstract: The invention provides a semiconductor package. The semiconductor package includes a substrate. A first conductive trace is disposed on the substrate. A solder resistance layer is disposed on the substrate, having an extending portion covering a portion of the first conductive trace, wherein a width of the extending portion of the solder resistance layer is larger than that of the portion of the first conductive trace. A semiconductor die is disposed over the first conductive trace.

Abstract translation: 本发明提供一种半导体封装。 半导体封装包括衬底。 第一导电迹线设置在衬底上。 焊料电阻层设置在衬底上，具有覆盖第一导电迹线的一部分的延伸部分，其中阻焊层的延伸部分的宽度大于第一导电迹线部分的宽度。 半导体管芯设置在第一导电迹线上。

公开(公告)号：US08502377B2

公开(公告)日：2013-08-06

申请号：US13110935

申请日：2011-05-19

Applicant: Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

Inventor： Tzu-Hung Lin ,  Ching-Liou Huang ,  Thomas Matthew Gregorich

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05011 ,  H01L2224/0519 ,  H01L2224/05559 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/13014 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2224/131 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package substrate including a conductive pattern disposed on a die attach surface of the package substrate; at least one bumping trace inlaid into the conductive pattern; and at least one gap disposed along with the bumping trace in the conductive pattern to separate the bumping trace from a bulk portion of the conductive pattern. The bumping trace may have a lathy shape from a plan view and a width substantially between 10 μm and 40 μm and a length substantially between 70 μm and 130 μm, for example.

Abstract translation: 1.一种封装基板，包括设置在所述封装基板的芯片附着面上的导电图案; 至少一个凸起轨迹嵌入到导电图案中; 以及与导电图案中的凸起轨迹一起布置的至少一个间隙，以将凸起迹线与导电图案的主体部分分离。 凸起迹线可以具有从平面图和宽度基本上在10um到40um之间的宽度，并且具有基本上在70μm和130μm之间的长度。