公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

申请人： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

发明人： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC分类号： H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

摘要： Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US09876016B2

公开(公告)日：2018-01-23

申请号：US13996523

申请日：2011-12-30

申请人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

发明人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC分类号： H01L27/092 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L23/485

CPC分类号： H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

公开(公告)号：US20130320456A1

公开(公告)日：2013-12-05

申请号：US13995678

申请日：2011-12-22

申请人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

发明人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC分类号： H01L21/28 ,  H01L27/085

CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

摘要翻译： 描述门对齐的触点和形成栅极对准触点的方法。 例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。 栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。 形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。 形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。 在形成多个接触插塞之后形成多个触点和多个栅极结构。

公开(公告)号：US09716037B2

公开(公告)日：2017-07-25

申请号：US13995678

申请日：2011-12-22

申请人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

发明人： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC分类号： H01L21/768 ,  H01L27/088 ,  H01L21/306 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

摘要： Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US20140159159A1

公开(公告)日：2014-06-12

申请号：US13996523

申请日：2011-12-30

申请人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

发明人： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC分类号： H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

摘要翻译： 描述了环绕的源极/漏极沟槽接触结构。 多个半导体鳍片从半导体衬底延伸。 沟道区域设置在每个鳍片之间的一对源极/漏极区域之间。 外延半导体层覆盖源极/漏极区域上的每个鳍的顶表面和侧壁表面，限定相邻鳍片之间的高纵横比间隙。 一对源/漏沟槽触点电耦合到外延半导体层。 源极/漏极沟槽触点包括保形金属层和填充金属。 保形金属层符合外延半导体层。 填充金属包括塞子和阻挡层，其中塞子填充形成在鳍片和保形金属层之上的接触沟槽，并且阻挡层对插塞进行引线以防止共形金属层材料和插塞材料的相互扩散。

公开(公告)号：US09728464B2

公开(公告)日：2017-08-08

申请号：US13560513

申请日：2012-07-27

申请人： Glenn A. Glass ,  Daniel B. Aubertine ,  Anand S. Murthy ,  Gaurav Thareja ,  Tahir Ghani

发明人： Glenn A. Glass ,  Daniel B. Aubertine ,  Anand S. Murthy ,  Gaurav Thareja ,  Tahir Ghani

IPC分类号： H01L21/335 ,  H01L21/8238 ,  H01L29/10

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/8258 ,  H01L29/1054

摘要： Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20170047416A1

公开(公告)日：2017-02-16

申请号：US15335281

申请日：2016-10-26

申请人： Annalisa Cappellani ,  Abhijit Jayant Pethe ,  Tahir Ghani ,  Harry Gomez

发明人： Annalisa Cappellani ,  Abhijit Jayant Pethe ,  Tahir Ghani ,  Harry Gomez

IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L29/42392 ,  B82Y10/00 ,  H01L21/30604 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： Strained gate-all-around semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional channel region is disposed above the insulating structure. Source and drain regions are disposed on either side of the three-dimensional channel region and on an epitaxial seed layer. The epitaxial seed layer is composed of a semiconductor material different from the three-dimensional channel region and disposed on the insulating structure. A gate electrode stack surrounds the three-dimensional channel region with a portion disposed on the insulating structure and laterally adjacent to the epitaxial seed layer.

摘要翻译： 描述了形成在全局或局部隔离的基板上的应变门全面半导体器件。 例如，半导体器件包括半导体衬底。 绝缘结构设置在半导体衬底之上。 三维沟道区设置在绝缘结构的上方。 源极和漏极区域设置在三维沟道区域的两侧和外延晶种层上。 外延种子层由不同于三维沟道区的半导体材料构成，并且设置在绝缘结构上。 栅极电极堆叠围绕三维沟道区域，其中设置在绝缘结构上并且横向邻近外延籽晶层的部分。

公开(公告)号：US20170004998A1

公开(公告)日：2017-01-05

申请号：US15266819

申请日：2016-09-15

申请人： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

发明人： Abhijit Jayant Pethe ,  Tahir Ghani ,  Mark Bohr ,  Clair Webb ,  Harry Gomez ,  Annalisa Cappellani

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/28 ,  H01L23/522 ,  H01L29/66 ,  H01L21/311

CPC分类号： H01L21/76897 ,  H01L21/28008 ,  H01L21/31111 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/53257 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/785

摘要： Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

摘要翻译： 描述了设置在门的有效部分上的栅极接触结构以及形成这种栅极接触结构的方法。 例如，半导体结构包括具有有源区和隔离区的衬底。 栅极结构具有设置在有源区上方的部分和设置在衬底的隔离区上方的部分。 源极和漏极区域设置在衬底的有源区域中，位于栅极结构的位于有源区域之上的部分的任一侧上。 栅极接触结构设置在栅极结构的设置在衬底的有源区上方的部分上。

公开(公告)号：US20150171218A1

公开(公告)日：2015-06-18

申请号：US14108265

申请日：2013-12-16

申请人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

发明人： Joseph M. Steigerwald ,  Tahir Ghani ,  Jenny Hu ,  Ian R. C. Post

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L29/7831 ,  H01L21/28114 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/0886 ,  H01L29/42372 ,  H01L29/42376 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78645

摘要： Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus includes a semiconductor substrate, a channel body disposed on the semiconductor substrate, a first gate electrode having a first thickness coupled with the channel body and a second gate electrode having a second thickness coupled with the channel body, wherein the first thickness is greater than the second thickness. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了多阈值电压装置及相关联的技术和配置。 在一个实施例中，一种装置包括半导体衬底，设置在半导体衬底上的沟道体，具有与沟道本体耦合的第一厚度的第一栅电极和具有与沟道本体耦合的第二厚度的第二栅电极，其中， 第一厚度大于第二厚度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20140264679A1

公开(公告)日：2014-09-18

申请号：US13994716

申请日：2013-03-15

申请人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

发明人： Kevin J. Lee ,  Tahir Ghani ,  Joseph M. Steigerwald ,  John H. Epple ,  Yih Wang

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/222 ,  H01L27/226 ,  H01L43/08

摘要： An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-MRAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) with an upper MTJ layer, lower MTJ layer, and tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. In an embodiment the first and second ILDs directly contact one another. Other embodiments are described herein.

摘要翻译： 实施例将逻辑芯片内的诸如自旋转矩传递磁阻随机存取存储器（STT-MRAM）的存储器集成。 STT-MRAM包括具有上部MTJ层，较低MTJ层和直接接触上层MTJ层和下层MTJ层的隧道势垒的磁隧道结（MTJ）; 其中上MTJ层包括上MTJ层侧壁，下MTJ层包括水平地偏离上MTJ层的下MTJ侧壁。 另一个实施例包括包含MTJ的存储区域和位于衬底上的逻辑区域; 其中水平面与MTJ相邻，邻近MTJ的第一层间电介质（ILD）材料和包含在逻辑区域中的第二ILD材料，第一和第二ILD材料彼此不相等。 在一个实施例中，第一和第二ILD直接彼此接触。 本文描述了其它实施例。