公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

Inventor： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20090283922A1

公开(公告)日：2009-11-19

申请号：US11965317

申请日：2007-12-27

Applicant: Willy Rachmady ,  Justin S. Sandford ,  Oleg Golonzka

Inventor： Willy Rachmady ,  Justin S. Sandford ,  Oleg Golonzka

IPC: H01L21/311 ,  H01L23/29

CPC classification number: H01L21/28247 ,  H01L21/28061 ,  H01L21/31111 ,  H01L29/4966 ,  H01L29/7847

Abstract: In some embodiments an etchstop layer is deposited over a transistor that has been encapsulated by a high-K film, a silicon nitride is deposited over the deposited etchstop layer, the silicon nitride is removed, and the etchstop layer is removed. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，蚀刻阻挡层沉积在已经被高K膜封装的晶体管上，氮化硅沉积在沉积的蚀刻阻挡层上，氮化硅被去除，并且蚀刻阻挡层被去除。 描述和要求保护其他实施例。

公开(公告)号：US20240304619A1

公开(公告)日：2024-09-12

申请号：US18181155

申请日：2023-03-09

Applicant: Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Tao Chu ,  Feng Zhang ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka

Inventor： Guowei Xu ,  Chiao-Ti Huang ,  Robin Chao ,  Tao Chu ,  Feng Zhang ,  Yang Zhang ,  Biswajeet Guha ,  Oleg Golonzka

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L29/0665 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/778 ,  H01L29/7851

Abstract: An IC device includes a backside FTI separating a first transistor from a second transistor. The FTI may be between a source region of the first transistor and a drain region of the second transistor. The source region of the first transistor and the drain region of the second transistor may be different portions of a semiconductor structure, e.g., a fin or nanoribbon. The IC device may also include a frontside metal layer. The semiconductor structure may have a first surface and a second surface opposing the first surface. The first surface of the semiconductor structure may be closer to the metal layer and larger than the second surface of the semiconductor structure. The FTI may have a first surface and a second surface opposing the first surface. The first surface of the FTI may be closer to the metal layer but smaller than the second surface of the FTI.

公开(公告)号：US20140252464A1

公开(公告)日：2014-09-11

申请号：US14284808

申请日：2014-05-22

Applicant: Bernhard Sell ,  Oleg Golonzka

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20080128763A1

公开(公告)日：2008-06-05

申请号：US11607549

申请日：2006-11-30

Applicant: Willy Rachmady ,  Vijay Ramachandrarao ,  Oleg Golonzka ,  Arnel M. Fajardo

Inventor： Willy Rachmady ,  Vijay Ramachandrarao ,  Oleg Golonzka ,  Arnel M. Fajardo

IPC: H01L29/78 ,  H01L21/04 ,  C09K13/00

CPC classification number: H01L21/32134 ,  H01L21/76834 ,  H01L21/76897

Abstract: A transistor comprises a gate (110) comprising a gate electrode (111) and a gate dielectric (112), an electrically insulating cap (120, 720) over the gate, and a source/drain contact (130) adjacent to the gate. The electrically insulating cap prevents electrical contact between the gate and the source/drain contact. In one embodiment, the electrically insulating cap is formed in a trench (160, 660) that is self-aligned to the gate and that is created by the removal of a sacrificial cap using an aqueous solution comprising a carboxylic acid and a corrosion inhibitor.

Abstract translation: 晶体管包括栅极（110），栅极（110）包括栅极电极（111）和栅极电介质（112），栅极上的电绝缘盖（120,720）以及与栅极相邻的源极/漏极接触（130）。 电绝缘帽防止栅极和源极/漏极接触之间的电接触。 在一个实施例中，电绝缘帽形成在与浇口自对准的沟槽（160,660）中，并且通过使用包含羧酸和腐蚀抑制剂的水溶液去除牺牲帽而产生。

公开(公告)号：US20060003597A1

公开(公告)日：2006-01-05

申请号：US10881052

申请日：2004-06-30

Applicant: Oleg Golonzka ,  Ajay Sharma ,  Nadia Rahhal-Orabi ,  Anthony Amour ,  James Chung

Inventor： Oleg Golonzka ,  Ajay Sharma ,  Nadia Rahhal-Orabi ,  Anthony Amour ,  James Chung

IPC: H01L21/336 ,  H01L21/31

CPC classification number: H01L21/0217 ,  H01L21/0214 ,  H01L21/3143 ,  H01L21/3148 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/66636 ,  H01L29/7843

Abstract: The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.

Abstract translation: 提高了集成电路的NMOS和PMOS区域的性能。 本发明的实施例包括形成针对n掺杂区域上的n掺杂区域优化的第一电介质层，并形成对p掺杂区域上的p掺杂区域优化的第二介电层。

公开(公告)号：US10804460B2

公开(公告)日：2020-10-13

申请号：US16097801

申请日：2016-07-01

Applicant: MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani ,  Intel Corporation

Inventor： MD Tofizur Rahman ,  Christopher J. Wiegand ,  Brian Maertz ,  Daniel G. Ouellette ,  Kevin P. O'Brien ,  Kaan Oguz ,  Brian S. Doyle ,  Mark L. Doczy ,  Daniel B. Bergstrom ,  Justin S. Brockman ,  Oleg Golonzka ,  Tahir Ghani

IPC: H01L29/82 ,  H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  G11C11/16 ,  H01L43/02

Abstract: Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US09716037B2

公开(公告)日：2017-07-25

申请号：US13995678

申请日：2011-12-22

Applicant: Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

Inventor： Oleg Golonzka ,  Swaminathan Sivakumar ,  Charles H. Wallace ,  Tahir Ghani

IPC: H01L21/768 ,  H01L27/088 ,  H01L21/306 ,  H01L27/02 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

公开(公告)号：US08803245B2

公开(公告)日：2014-08-12

申请号：US12215991

申请日：2008-06-30

Applicant: Bernhard Sell ,  Oleg Golonzka

Inventor： Bernhard Sell ,  Oleg Golonzka

IPC: H01L21/02

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IID disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：US20140159159A1

公开(公告)日：2014-06-12

申请号：US13996523

申请日：2011-12-30

Applicant: Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

Inventor： Joseph Steigerwald ,  Tahir Ghani ,  Oleg Golonzka

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

Abstract translation: 描述了环绕的源极/漏极沟槽接触结构。 多个半导体鳍片从半导体衬底延伸。 沟道区域设置在每个鳍片之间的一对源极/漏极区域之间。 外延半导体层覆盖源极/漏极区域上的每个鳍的顶表面和侧壁表面，限定相邻鳍片之间的高纵横比间隙。 一对源/漏沟槽触点电耦合到外延半导体层。 源极/漏极沟槽触点包括保形金属层和填充金属。 保形金属层符合外延半导体层。 填充金属包括塞子和阻挡层，其中塞子填充形成在鳍片和保形金属层之上的接触沟槽，并且阻挡层对插塞进行引线以防止共形金属层材料和插塞材料的相互扩散。