公开(公告)号：US20170069596A1

公开(公告)日：2017-03-09

申请号：US15121759

申请日：2014-03-27

Applicant: Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

Inventor： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L25/065 ,  H01L29/24 ,  H01L29/20 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  G06F1/1652 ,  G09F9/301 ,  G09G3/3648 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/4985 ,  H01L25/00 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002

Abstract: Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。 可以依次处理多材料堆叠，以在单个柔性SOC中形成多个集成电路（IC）装置。 通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点位于SOC的公共背面中。 堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。 以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US09105839B2

公开(公告)日：2015-08-11

申请号：US14333180

申请日：2014-07-16

Applicant: Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L21/00 ,  H01L43/12 ,  H01L29/82 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Abstract translation: 描述具有偏移单元的垂直自旋转移转矩存储器（STTM）器件和制造具有偏置单元的垂直STTM器件的方法。 例如，自旋转矩传递存储器（STTM）阵列包括设置在衬底上方并且仅具有第一STTM器件的第一负载线。 STTM阵列还包括设置在基板上方的第二负载线，与第一负载线相邻，并且仅具有第二STTM器件，与第一STTM器件非共面的第二STTM器件。

公开(公告)号：US20150091067A1

公开(公告)日：2015-04-02

申请号：US14040574

申请日：2013-09-27

Applicant: Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

Inventor： Ravi Pillarisetty ,  Brian S. Doyle ,  Elijah V. Karpov ,  David L. Kencke ,  Uday Shah ,  Charles C. Kuo ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/2436 ,  H01L29/66477 ,  H01L29/66568 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1616 ,  H01L2029/7858

Abstract: An insulating layer is deposited over a transistor structure. The transistor structure comprises a gate electrode over a device layer on a substrate. The transistor structure comprises a first contact region and a second contact region on the device layer at opposite sides of the gate electrode. A trench is formed in the first insulating layer over the first contact region. A metal-insulator phase transition material layer with a S-shaped IV characteristic is deposited in the trench or in the via of the metallization layer above on the source side.

Abstract translation: 在晶体管结构上沉积绝缘层。 晶体管结构包括位于衬底上的器件层上的栅电极。 晶体管结构包括在栅电极的相对侧的器件层上的第一接触区域和第二接触区域。 在第一接触区域上的第一绝缘层中形成沟槽。 具有S形IV特性的金属 - 绝缘体相变材料层沉积在源极侧上方的金属化层的沟槽或通路中。

公开(公告)号：US20140374689A1

公开(公告)日：2014-12-25

申请号：US13925951

申请日：2013-06-25

Applicant: Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

Inventor： Elijah V. Karpov ,  Brian S. Doyle ,  Uday Shah ,  Robert S. Chau

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/1266

Abstract: Conductive oxide random access memory (CORAM) cells and methods of fabricating CORAM cells are described. For example, a material layer stack for a memory element includes a first conductive electrode. An insulating layer is disposed on the first conductive oxide and has an opening with sidewalls therein that exposes a portion of the first conductive electrode. A conductive oxide layer is disposed in the opening, on the first conductive electrode and along the sidewalls of the opening. A second electrode is disposed in the opening, on the conductive oxide layer.

Abstract translation: 描述了导电氧化物随机存取存储器（CORAM）单元和制造CORAM单元的方法。 例如，用于存储元件的材料层堆叠包括第一导电电极。 绝缘层设置在第一导电氧化物上并且具有露出第一导电电极的一部分的侧壁的开口。 导电氧化物层设置在开口中，在第一导电电极上并且沿着开口的侧壁。 第二电极设置在开口中，在导电氧化物层上。

公开(公告)号：US20140204661A1

公开(公告)日：2014-07-24

申请号：US13995631

申请日：2011-12-22

Applicant: Brian S. Doyle ,  Arijit Raychowdhury ,  Yong Ju Lee ,  Charles C. Kuo ,  Kaan Oguz ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

Inventor： Brian S. Doyle ,  Arijit Raychowdhury ,  Yong Ju Lee ,  Charles C. Kuo ,  Kaan Oguz ,  David L. Kencke ,  Robert S. Chau ,  Roksana Golizadeh Mojarad

IPC: H01L43/02 ,  G11C11/16

CPC classification number: H01L43/02 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/228 ,  H01L43/08

Abstract: A magnetic memory having memory elements each with two magnetic tunneling junction (MTJ) devices is disclosed. The devices in each element are differentially programmed with complementary data. The devices for each element are stacked one above the other so that the element requires no more substrate area than a single MTJ device.

Abstract translation: 公开了具有各自具有两个磁隧道结（MTJ）装置的存储元件的磁存储器。 每个元件中的器件都用补充数据进行差分编程。 每个元件的器件彼此层叠，使得元件不需要比单个MTJ器件更多的衬底面积。

公开(公告)号：US08786040B2

公开(公告)日：2014-07-22

申请号：US13723866

申请日：2012-12-21

Applicant: Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L27/22

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

Abstract translation: 描述具有偏移单元的垂直自旋转移转矩存储器（STTM）器件和制造具有偏置单元的垂直STTM器件的方法。 例如，自旋转矩传递存储器（STTM）阵列包括设置在衬底上方并且仅具有第一STTM器件的第一负载线。 STTM阵列还包括设置在基板上方的第二负载线，与第一负载线相邻，并且仅具有第二STTM器件，与第一STTM器件非共面的第二STTM器件。

公开(公告)号：US20140175583A1

公开(公告)日：2014-06-26

申请号：US13723866

申请日：2012-12-21

Applicant: Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

Inventor： Brian S. Doyle ,  David L. Kencke ,  Charles C. Kuo ,  Uday Shah ,  Kaan Oguz ,  Mark L. Doczy ,  Satyarth Suri ,  Clair Webb

IPC: H01L29/82 ,  H01L29/66

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/1659 ,  H01L27/222 ,  H01L27/228 ,  H01L29/66007 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Perpendicular spin transfer torque memory (STTM) devices having offset cells and methods of fabricating perpendicular STTM devices having offset cells are described. For example, a spin torque transfer memory (STTM) array includes a first load line disposed above a substrate and having only a first STTM device. The STTM array also includes a second load line disposed above the substrate, adjacent the first load line, and having only a second STTM device, the second STTM device non-co-planar with the first STTM device.

公开(公告)号：US20140170920A1

公开(公告)日：2014-06-19

申请号：US13715012

申请日：2012-12-14

Applicant: Sasikanth Manipatruni ,  Shawna M. Liff ,  Brian S. Doyle ,  Vivek K. Singh

Inventor： Sasikanth Manipatruni ,  Shawna M. Liff ,  Brian S. Doyle ,  Vivek K. Singh

IPC: D03D1/00 ,  D04H13/00

CPC classification number: D03D1/0088 ,  D02G3/441 ,  D04H13/00 ,  D10B2401/18 ,  Y10T442/3049 ,  Y10T442/3057 ,  Y10T442/3976 ,  Y10T442/603 ,  Y10T442/696

Abstract: Flexible electronically functional fabrics are described that allow for the placement of electronic functionality in flexible substrates such as traditional fabrics. The fabrics can be made using flexible electronically functional fibers or a combination of electronically functional fibers and textile fibers. Electronic devices can be incorporated into the fabric to give it full computing capabilities.

Abstract translation: 描述了柔性电子功能织物，其允许将电子功能放置在诸如传统织物的柔性衬底中。 织物可以使用柔性电子功能纤维或电子功能性纤维和纺织纤维的组合制成。 电子设备可以结合到织物中，为其提供全面的计算能力。

公开(公告)号：US20140166080A1

公开(公告)日：2014-06-19

申请号：US13717186

申请日：2012-12-17

Applicant: Aleksandar Aleksov ,  Brian S. Doyle ,  Ravindranath V. Mahajan

Inventor： Aleksandar Aleksov ,  Brian S. Doyle ,  Ravindranath V. Mahajan

IPC: H01L31/048 ,  H01L31/0203 ,  H01G9/20 ,  H01L31/0232

CPC classification number: H01L31/0488 ,  H01L27/301 ,  H02S20/26 ,  Y02B10/10 ,  Y02E10/50

Abstract: An apparatus for collecting solar energy, including a first panel, wherein the first panel allows at least 50% of incident light having a wavelength in the range of 1 nm to 1,500 nm to pass through said panel and a second panel, wherein the second panel allows at least 50% of incident light having a wavelength in the range of 410 nm to 650 nm to pass through said panel. A photovoltaic cell is disposed between the first panel and second panel, which includes a first electrode disposed adjacent to the first panel, a second electrode disposed adjacent to the second panel, a photovoltaic component contacting the first and second electrodes. The photovoltaic component absorbs at least 50% of light having a wavelength in one of the following ranges: greater than 650 nm, less than 410 nm and combinations thereof.

Abstract translation: 一种用于收集太阳能的装置，包括第一面板，其中所述第一面板允许波长在1nm至1,500nm范围内的至少50％的入射光通过所述面板和第二面板，其中所述第二面板 允许波长在410nm至650nm范围内的至少50％的入射光通过所述面板。 光伏电池设置在第一面板和第二面板之间，其包括邻近第一面板设置的第一电极，邻近第二面板设置的第二电极，与第一和第二电极接触的光伏组件。 光伏组件吸收至少50％的具有以下范围之一的波长的光：大于650nm，小于410nm及其组合。

公开(公告)号：US20140084399A1

公开(公告)日：2014-03-27

申请号：US13629162

申请日：2012-09-27

Applicant: Mark L. Doczy ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

Inventor： Mark L. Doczy ,  Kaan Oguz ,  Brian S. Doyle ,  Robert S. Chau

IPC: H01L29/82 ,  H01L21/02

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/30 ,  H01F10/329 ,  H01F41/307 ,  H01L27/228 ,  H01L43/12

Abstract: Spin transfer torque memory (STTM) devices with topographically smooth electrodes and methods of fabricating STTM devices with topographically smooth electrodes are described. For example, a material layer stack for a magnetic tunneling junction includes a topographically smooth bottom electrode, a topographically smooth dielectric layer disposed above the bottom electrode, and a free magnetic layer disposed above the topographically smooth dielectric layer.

Abstract translation: 描述了具有地形平滑电极的自旋转移转矩记忆（STTM）装置和制造具有地形平滑电极的STTM装置的方法。 例如，用于磁隧道结的材料层堆叠包括地形上平滑的底部电极，设置在底部电极上方的地形平滑的电介质层和设置在地形平滑介电层上方的自由磁性层。