公开(公告)号：US20190140166A1

公开(公告)日：2019-05-09

申请号：US16097801

申请日：2016-07-01

申请人： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahhir GHANI ,  Intel Corporation

发明人： MD Tofizur RAHMAN ,  Christopher J. WIEGAND ,  Brian MAERTZ ,  Daniel G. OUELLETTE ,  Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Daniel B. BERGSTROM ,  Justin S. BROCKMAN ,  Oleg GOLONZKA ,  Tahir GHANI

IPC分类号： H01L43/12 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

摘要： Material layer stack structures to provide a magnetic tunnel junction (MTJ) having improved perpendicular magnetic anisotropy (PMA) characteristics. In an embodiment, a free magnetic layer of the material layer stack is disposed between a tunnel barrier layer and a cap layer of magnesium oxide (Mg). The free magnetic layer includes a Cobalt-Iron-Boron (CoFeB) body substantially comprised of a combination of Cobalt atoms, Iron atoms and Boron atoms. A first Boron mass fraction of the CoFeB body is equal to or more than 25% (e.g., equal to or more than 27%) in a first region which adjoins an interface of the free magnetic layer with the tunnel barrier layer. In another embodiment, the first Boron mass fraction is more than a second Boron mass fraction in a second region of the CoFeB body which adjoins an interface of the free magnetic layer with the cap layer.

公开(公告)号：US20140177326A1

公开(公告)日：2014-06-26

申请号：US13725235

申请日：2012-12-21

申请人： Brian S. DOYLE ,  Charles C. KUO ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Uday SHAH

发明人： Brian S. DOYLE ,  Charles C. KUO ,  David L. KENCKE ,  Roksana GOLIZADEH MOJARAD ,  Uday SHAH

IPC分类号： H01L43/02 ,  G11C11/16 ,  H01L43/12

CPC分类号： H01L43/02 ,  G11C11/155 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： Spin transfer torque memory (STTM) devices incorporating a field plate for application of an electric field to reduce a critical current required for transfer torque induced magnetization switching. Embodiments utilize not only current-induced magnetic filed or spin transfer torque, but also electric field induced manipulation of magnetic dipole orientation to set states in a magnetic device element (e.g., to write to a memory element). An electric field generated by a voltage differential between an MTJ electrode and the field plate applies an electric field to a free magnetic layer of a magnetic tunneling junction (MTJ) to modulate one or more magnetic properties over at least a portion of the free magnetic layer.

摘要翻译： 具有用于施加电场的场板的旋转转矩存储器（STTM）装置，以减少传递转矩感应磁化切换所需的临界电流。 实施例不仅利用电流感应磁场或自旋转移转矩，还利用电场诱导的磁偶极取向的操纵来设置磁性器件元件中的状态（例如，写入存储元件）。 由MTJ电极和场板之间的电压差产生的电场向磁性隧道结（MTJ）的自由磁性层施加电场，以在至少一部分自由磁性层上调制一个或多个磁性能 。

公开(公告)号：US20140166981A1

公开(公告)日：2014-06-19

申请号：US13719093

申请日：2012-12-18

申请人： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

发明人： Brian S. DOYLE ,  Roza KOTLYAR ,  Uday SHAH ,  Charles C. KUO

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/66

CPC分类号： H01L29/7827 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02636 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66431 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  Y10S977/762

摘要： Vertically oriented nanowire transistors including semiconductor layers or gate electrodes having compositions that vary over a length of the transistor. In embodiments, transistor channel regions are compositionally graded, or layered along a length of the channel to induce strain, and/or include a high mobility injection layer. In embodiments, a gate electrode stack including a plurality of gate electrode materials is deposited to modulate the gate electrode work function along the gate length.

摘要翻译： 垂直取向的纳米线晶体管包括具有在晶体管的长度上变化的组成的半导体层或栅电极。 在实施例中，晶体管沟道区域沿着沟道的长度成分地分级或分层以诱导应变，和/或包括高迁移率注入层。 在实施例中，沉积包括多个栅电极材料的栅极电极堆叠以沿着栅极长度调制栅电极功函数。

公开(公告)号：US20170069596A1

公开(公告)日：2017-03-09

申请号：US15121759

申请日：2014-03-27

申请人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

发明人： Ravi PILLARISETTY ,  Sansaptak DASGUPTA ,  Niloy MUKHERJEE ,  Brian S. DOYLE ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC分类号： H01L25/065 ,  H01L29/24 ,  H01L29/20 ,  H01L23/498 ,  H01L25/00

CPC分类号： H01L25/0652 ,  G06F1/1652 ,  G09F9/301 ,  G09G3/3648 ,  H01L21/8221 ,  H01L21/8258 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49811 ,  H01L23/4985 ,  H01L25/00 ,  H01L25/50 ,  H01L27/0688 ,  H01L29/2003 ,  H01L29/24 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2924/0002

摘要： Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

摘要翻译： 本公开的实施例描述了芯片上的多设备灵活系统（SOC）以及用于制造这种SOC的方法。 可以依次处理多材料堆叠，以在单个柔性SOC中形成多个集成电路（IC）装置。 通过从单个堆叠形成IC器件，可以通过单个金属化工艺为多个器件形成触点，并且可以将这些触点位于SOC的公共背面中。 堆叠层可以根据处理温度进行排序和处理，使得较早进行较高温度处理。 以这种方式，堆叠的中间层可以屏蔽一些堆叠层与处理堆叠的上层相关联的升高的处理温度。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20200227477A1

公开(公告)日：2020-07-16

申请号：US16631156

申请日：2017-09-13

申请人： Intel Corporation

发明人： Prashant MAJHI ,  Ravi PILLARISETTY ,  Elijah V. KARPOV ,  Brian S. DOYLE ,  Abhishek A. SHARMA

IPC分类号： H01L27/24 ,  H01L45/00 ,  H01L27/22 ,  H01L43/12 ,  H01L43/02

摘要： Embedded non-volatile memory structures having selector elements with ballast are described. In an example, a memory device includes a word line. A selector element is above the word line. The selector element includes a selector material layer and a ballast material layer different than the selector material layer. A bipolar memory element is above the word line. A conductive electrode is between the elector element and the bipolar memory element. A bit line is above the word line.

公开(公告)号：US20170271576A1

公开(公告)日：2017-09-21

申请号：US15503680

申请日：2014-09-26

申请人： Intel Corporation

发明人： Kevin P. O'BRIEN ,  Kaan OGUZ ,  Brian S. DOYLE ,  Mark L. DOCZY ,  Charles C. KUO ,  Robert S. CHAU

IPC分类号： H01L43/08 ,  H01L43/12 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10

CPC分类号： H01L43/08 ,  G11C11/161 ,  G11C11/1659 ,  H01F10/3295 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

摘要： A material layer stack for a magnetic tunneling junction, the material layer stack including a fixed magnetic layer; a dielectric layer; a free magnetic layer; and an amorphous electrically-conductive seed layer, wherein the fixed magnetic layer is disposed between the dielectric layer and the seed layer. A non-volatile memory device including a material stack including an amorphous electrically-conductive seed layer; and a fixed magnetic layer juxtaposed and in contact with the seed layer. A method including forming an amorphous seed layer on a first electrode of a memory device; forming a material layer stack on the amorphous seed layer, the material stack including a dielectric layer disposed between a fixed magnetic layer and a free magnetic layer, wherein the fixed magnetic layer.

公开(公告)号：US20160291641A1

公开(公告)日：2016-10-06

申请号：US15037639

申请日：2013-12-26

申请人： INTEL CORPORATION

发明人： Brian S. DOYLE ,  Han Wui THEN ,  Valluri RAO ,  Niloy MUKHERJEE ,  Robert S. CHAU ,  Ravi PILLARISETTY

IPC分类号： G06F1/16 ,  H04M1/02 ,  H05K3/30 ,  H05K1/02 ,  H05K3/46

CPC分类号： G06F1/1652 ,  G06F1/1626 ,  G06F1/1643 ,  G06F1/1656 ,  G06F2203/04102 ,  G06F2203/04103 ,  G09F9/00 ,  G09G3/2092 ,  G09G2300/0426 ,  G09G2380/02 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1266 ,  H04M1/0268 ,  H05K1/028 ,  H05K1/0296 ,  H05K3/30 ,  H05K3/4682

摘要： A flexible electronic computing device is described. In one embodiment, a flexible display is formed on a flexible substrate. A plurality of electronic components are attached to the flexible substrate. A plurality of conductive signal lines are formed on the flexible substrate, the signal lines electrically coupling the electronic components to the flexible display.

摘要翻译： 描述了一种灵活的电子计算设备。 在一个实施例中，柔性显示器形成在柔性基板上。 多个电子部件附接到柔性基板。 多个导电信号线形成在柔性基板上，信号线将电子部件电耦合到柔性显示器。

公开(公告)号：US20220199801A1

公开(公告)日：2022-06-23

申请号：US17132996

申请日：2020-12-23

申请人： Intel Corporation

发明人： Prashant MAJHI ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Brian S. DOYLE ,  Urusa ALAAN ,  Van H. LE ,  Elijah V. KARPOV ,  Kaan OGUZ ,  Arnab SEN GUPTA

IPC分类号： H01L29/66 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/683 ,  H01L29/78

摘要： Embodiments disclosed herein include a semiconductor devices with back end of line (BEOL) transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate and a BEOL stack over the semiconductor substrate. In an embodiment, a field effect transistor (FET) is embedded in the BEOL stack. In an embodiment, the FET comprises a channel, a gate dielectric over the channel, where the gate dielectric is single crystalline, a gate electrode over the gate dielectric, and a source electrode and a drain electrode passing through the gate dielectric to contact the channel.

公开(公告)号：US20220199609A1

公开(公告)日：2022-06-23

申请号：US17133595

申请日：2020-12-23

申请人： Intel Corporation

发明人： Urusa ALAAN ,  Abhishek A. SHARMA ,  Charles C. KUO ,  Benjamin ORR ,  Nicholas THOMSON ,  Ayan KAR ,  Arnab SEN GUPTA ,  Kaan OGUZ ,  Brian S. DOYLE ,  Prashant MAJHI ,  Van H. LE ,  Elijah V. KARPOV

IPC分类号： H01L27/02 ,  H02H9/04

摘要： Embodiments disclosed herein include semiconductor devices with electrostatic discharge (ESD) protection of the transistor devices. In an embodiment, a semiconductor device comprises a semiconductor substrate, where a transistor device is provided on the semiconductor substrate. In an embodiment, the semiconductor device further comprises a stack of routing layers over the semiconductor substrate, and a diode in the stack of routing layers. In an embodiment, the diode is configured to provide electrostatic discharge (ESD) protection to the transistor device.

公开(公告)号：US20220181335A1

公开(公告)日：2022-06-09

申请号：US17673670

申请日：2022-02-16

申请人： Intel Corporation

发明人： Abhishek A. SHARMA ,  Brian S. DOYLE ,  Ravi PILLARISETTY ,  Prashant MAJHI ,  Elijah V. KARPOV

IPC分类号： H01L27/1159 ,  G11C11/22 ,  H01L29/51 ,  H01L29/78

摘要： A ferroelectric field-effect transistor (FeFET) includes first and second gate electrodes, source and drain regions, a semiconductor region between and physically connecting the source and drain regions, a first gate dielectric between the semiconductor region and the first gate electrode, and a second gate dielectric between the semiconductor region and the second gate electrode. The first gate dielectric includes a ferroelectric dielectric. In an embodiment, a memory cell includes this FeFET, with the first gate electrode being electrically connected to a wordline and the drain region being electrically connected to a bitline. In another embodiment, a memory array includes wordlines extending in a first direction, bitlines extending in a second direction, and a plurality of such memory cells at crossing regions of the wordlines and the bitlines. In each memory cell, the wordline is a corresponding one of the wordlines and the bitline is a corresponding one of the bitlines.