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    Semiconductor Devices and Methods for Manufacturing the Same
    2.
    发明申请
    Semiconductor Devices and Methods for Manufacturing the Same 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20090032902A1

    公开(公告)日：2009-02-05

    申请号：US12249883

    申请日：2008-10-10

    申请人： Chul-Ho SHIN ,  Tae-Hong Kim

    发明人： Chul-Ho SHIN ,  Tae-Hong Kim

    IPC分类号： H01L23/58

    CPC分类号： H01L21/02323 ,  H01L21/0214 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/823462 ,  H01L21/823481

    摘要： Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere.

    摘要翻译： 公开了半导体装置及其制造方法。 一种示例性方法包括将具有氮氧化物层的第一衬底与在舟皿中具有氮化物层的第二衬底加载，并且通过将舟放置在炉中并在其上热处理来在第一衬底上形成氧氮化物层 氧气氛围。

    Semiconductor apparatus using ion beam
    3.
    发明申请
    Semiconductor apparatus using ion beam 审中-公开
    使用离子束的半导体装置

    公开(公告)号：US20080164819A1

    公开(公告)日：2008-07-10

    申请号：US12007187

    申请日：2008-01-08

    申请人： Sung-Wook Hwang ,  Yung Hee Yvette Lee ,  Chul-Ho Shin ,  Jin-Seok Lee

    发明人： Sung-Wook Hwang ,  Yung Hee Yvette Lee ,  Chul-Ho Shin ,  Jin-Seok Lee

    IPC分类号： G21K1/00 ,  H05H1/00 ,  G21K1/14

    CPC分类号： H01J37/305 ,  H01J27/024 ,  H01J37/08 ,  H01J37/3171 ,  H01J2237/0041 ,  H01J2237/061

    摘要： Provided is a semiconductor apparatus using an ion beam. The semiconductor apparatus may include a first grid to which a voltage applied. The voltage applied to the first grid may have the same potential level as that of a reference voltage applied to a wall portion of a plasma chamber in which plasma may be generated. The first grid may adjoin the plasma. Therefore, a potential level difference between the first grid and the wall portion of the plasma chamber may be zero, and thus the plasma may be stable.

    摘要翻译： 提供了使用离子束的半导体装置。 半导体装置可以包括施加电压的第一栅极。 施加到第一栅极的电压可以具有与施加到其中可能产生等离子体的等离子体室的壁部分的参考电压相同的电位电平。 第一个栅格可能与等离子体相邻。 因此，等离子体室的第一栅极和壁部之间的电位差可以为零，因此等离子体可以是稳定的。

    Method for fabricating a capacitor in a semiconductor memory device
    4.
    发明授权
    Method for fabricating a capacitor in a semiconductor memory device 失效
    在半导体存储器件中制造电容器的方法

    公开(公告)号：US06391714B2

    公开(公告)日：2002-05-21

    申请号：US09738296

    申请日：2000-12-18

    申请人： Chul-Ho Shin ,  U In Chung

    发明人： Chul-Ho Shin ,  U In Chung

    IPC分类号： H01L218242

    CPC分类号： H01L28/84 ,  H01L21/3143 ,  H01L27/10814 ,  H01L27/10855 ,  Y10T29/41

    摘要： A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed. Finally, after removal of the exposed spacer, the dielectric layer and a conductive layer for the upper electrode of the capacitor are formed in sequence. The method does not require any additional insulation layer evaporation process, since the interlayer insulation layer for formation of the reverse storage electrode could be used for formation of a gate contact of a logic region, without removal. Consequently, simplification of fabrication process for a capacitor is achieved.

    摘要翻译： 一种用于制造半导体存储器件的电容器的方法，其能够提供增加的电容而不降低分辨率，以及在形成用于电容器的下电极时不去除任何层间绝缘层，其中在形成存取晶体管 半导体衬底，用于使半导体衬底的表面平坦化的第一层间绝缘层和用于形成电容器下电极的第二层间绝缘层。 在形成用于通过蚀刻第一和第二层间绝缘层的一部分来暴露存取晶体管的一部分杂质扩散区的开口，在开口内形成间隔物。 此外，在将电容器下电极的导电层沉积到基板的表面上之后，进行平坦化处理直到间隔件的上表面的一部分露出。 最后，在去除暴露的间隔物之后，依次形成电介质层和用于电容器的上电极的导电层。 该方法不需要任何额外的绝缘层蒸发工艺，因为用于形成反向存储电极的层间绝缘层可用于形成逻辑区域的栅极接触而不去除。 因此，实现了电容器制造工艺的简化。

    Semiconductor devices and methods for manufacturing the same
    6.
    发明授权
    Semiconductor devices and methods for manufacturing the same 失效
    半导体器件及其制造方法

    公开(公告)号：US07452830B2

    公开(公告)日：2008-11-18

    申请号：US11191182

    申请日：2005-07-27

    申请人： Chul-Ho Shin ,  Tae-Hong Kim

    发明人： Chul-Ho Shin ,  Tae-Hong Kim

    IPC分类号： H01L29/94 ,  H01L21/31

    CPC分类号： H01L21/02323 ,  H01L21/0214 ,  H01L21/02255 ,  H01L21/3144 ,  H01L21/823462 ,  H01L21/823481

    摘要： Semiconductor devices and methods for manufacturing the same are disclosed. An example method includes loading a first substrate to be provided with an oxynitride layer along with a second substrate having a nitride layer in a boat, and forming the oxynitride layer on the first substrate by placing the boat into a furnace and thermally treating the boat under an oxygen atmosphere.

    摘要翻译： 公开了半导体装置及其制造方法。 一种示例性方法包括将具有氮氧化物层的第一衬底与在舟皿中具有氮化物层的第二衬底加载，并且通过将舟放置在炉中并在其上热处理来在第一衬底上形成氧氮化物层 氧气氛围。

    DRAM cell
    7.
    发明授权
    DRAM cell 失效
    DRAM单元

    公开(公告)号：US06855597B2

    公开(公告)日：2005-02-15

    申请号：US10413372

    申请日：2003-04-15

    申请人： Chul-Ho Shin ,  Kyeong-Koo Chi

    发明人： Chul-Ho Shin ,  Kyeong-Koo Chi

    IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10855 ,  H01L27/10885 ,  H01L28/91

    摘要： A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.

    摘要翻译： 制造DRAM单元的方法包括在衬底的给定区域上形成隔离层以限定具有多个线状子区域的有源区域; 在每个线状子区域中形成至少一对单元晶体管，每对单元晶体管具有公共漏极区域和相应的源极区域; 在每个公共漏极区域上形成位线焊盘和在每个源极区域上形成存储节点焊盘; 形成具有与字线平行的部分的位线保护层图案，覆盖位线焊盘; 并在存储节点垫上形成存储节点。 DRAM单元的存储节点与存储节点焊盘接触，并通过位焊盘保护层图案与位线焊盘电绝缘。

    Method for manufacturing a mask read only memory device
    8.
    发明授权
    Method for manufacturing a mask read only memory device 失效
    用于制造只读存储器件的方法

    公开(公告)号：US5200355A

    公开(公告)日：1993-04-06

    申请号：US792590

    申请日：1991-11-15

    申请人： Jeong-Hyeok Choi ,  Chul-Ho Shin

    发明人： Jeong-Hyeok Choi ,  Chul-Ho Shin

    IPC分类号： H01L21/8246 ,  H01L27/112

    CPC分类号： H01L27/1126 ,  H01L27/112

    摘要： A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.

    摘要翻译： 公开了一种用于制造高度集成的NAND和NOR逻辑掩模只读存储器（MROM）器件的方法。 在形成第一多晶硅层的半导体衬底的顶表面上，沿着字线以奇数或偶数的顺序形成栅电极的图案。 接下来，在衬底的顶表面上形成具有亚微米范围厚度的绝缘层。 然后覆盖光致抗蚀剂并执行回蚀刻工艺。 此后，选择性地蚀刻由回蚀处理和多晶硅层引起的暴露的绝缘层，以形成对应于绝缘层的厚度的字线间距。 因此，可以最小化相邻字线之间的间隔，并且可以充分地确保处理余量。

    A mask read only memory device
    10.
    发明授权
    A mask read only memory device 失效
    掩码只读存储器件

    公开(公告)号：US5317534A

    公开(公告)日：1994-05-31

    申请号：US981488

    申请日：1992-11-25

    申请人： Jeong-Hyeok Choi ,  Chul-Ho Shin

    发明人： Jeong-Hyeok Choi ,  Chul-Ho Shin

    IPC分类号： H01L21/8246 ,  H01L27/112 ,  G11C11/40

    CPC分类号： H01L27/1126 ,  H01L27/112

    摘要： A method for manufacturing highly integrated NAND and NOR logic mask read only memory (MROM) devices is disclosed. Over the top surface of a semiconductor substrate, where a first polysilicon layer is formed, a pattern of a gate electrode is formed along a word line in the order of odd numbers or even numbers. Next, an insulation layer having a thickness of a submicron range is formed over the top surface of the substrate. And then a photoresist is covered and an etch back process is performed. Thereafter, the exposed insulation layer caused by the etch back process and the polysilicon layer are selectively etched to form a word line spacing corresponding to a thickness of the insulation layer. Thus, spacing between adjacent word lines can be minimized and a process margin can be sufficiently ensured.

    摘要翻译： 公开了一种用于制造高度集成的NAND和NOR逻辑掩模只读存储器（MROM）器件的方法。 在形成第一多晶硅层的半导体衬底的顶表面上，沿着字线以奇数或偶数的顺序形成栅电极的图案。 接下来，在衬底的顶表面上形成具有亚微米范围厚度的绝缘层。 然后覆盖光致抗蚀剂并执行回蚀刻工艺。 此后，选择性地蚀刻由回蚀处理和多晶硅层引起的暴露的绝缘层，以形成对应于绝缘层的厚度的字线间距。 因此，可以最小化相邻字线之间的间隔，并且可以充分地确保处理余量。