公开(公告)号：US20130256915A1

公开(公告)日：2013-10-03

申请号：US13614590

申请日：2012-09-13

Applicant: Huei-Nuan Huang ,  Chun-Tang Lin ,  Chien-Feng Chan ,  Chi-Hsin Chiu

Inventor： Huei-Nuan Huang ,  Chun-Tang Lin ,  Chien-Feng Chan ,  Chi-Hsin Chiu

IPC: H01L25/07 ,  H01L21/58 ,  H01L21/60 ,  H01L21/56

CPC classification number: H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/26175 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06582 ,  H01L2924/15311 ,  H01L2224/73204 ,  H01L2224/32225 ,  H01L2924/00

Abstract: A semiconductor package includes a packaging substrate having a die attach area, a plurality of flow-guiding blocks disposed around an outer periphery of the die attach area, a first semiconductor element mounted on the die attach area, a second semiconductor element mounted on the first semiconductor element, and an underfill formed between the packaging substrate and the second semiconductor element. During filling of the underfill between the packaging substrate and the second semiconductor element, the flow-guiding blocks can guide a portion of the underfill to flow between the first semiconductor element and the second semiconductor element such that only one dispensing process is required for the underfill to completely encapsulate all conductive bumps used for flip-chip interconnection, thereby simplifying the fabrication process and improving the production efficiency.

Abstract translation: 半导体封装包括具有管芯附着区域的封装衬底，设置在管芯附接区域的外周周围的多个引流块，安装在管芯附着区域上的第一半导体元件，安装在管芯附接区域上的第二半导体元件 半导体元件和形成在封装基板和第二半导体元件之间的底部填充物。 在填充包装基板和第二半导体元件之间的底部填充物的过程中，导流块可以引导底部填充物的一部分在第一半导体元件和第二半导体元件之间流动，使得底部填充物仅需要一个分配过程 完全封装用于倒装芯片互连的所有导电凸块，从而简化制造工艺并提高生产效率。

公开(公告)号：US08519526B2

公开(公告)日：2013-08-27

申请号：US13112226

申请日：2011-05-20

Applicant: Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L23/48

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。

公开(公告)号：US08603911B2

公开(公告)日：2013-12-10

申请号：US13105338

申请日：2011-05-11

Applicant: Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

Inventor： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

IPC: H01L21/44 ,  H01L23/12 ,  H01L29/40

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract translation: 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

公开(公告)号：US20120223425A1

公开(公告)日：2012-09-06

申请号：US13105338

申请日：2011-05-11

Applicant: Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

Inventor： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

IPC: H01L23/498 ,  H01L21/768

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

Abstract: A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

Abstract translation: 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

公开(公告)号：US20120161301A1

公开(公告)日：2012-06-28

申请号：US13112226

申请日：2011-05-20

Applicant: Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

Inventor： Jung-Pang Huang ,  Hui-Min Huang ,  Kuan-Wei Chuang ,  Chun-Tang Lin ,  Yih-Jenn Jiang

IPC: H01L23/495 ,  H01L21/60 ,  H01L23/48

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L23/3121 ,  H01L23/36 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2924/014 ,  H01L2924/3511

Abstract: A semiconductor package includes: a chip having an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface; an encapsulant encapsulating the chip and having opposite first and second surfaces, the first surface being flush with the active surface of the chip; and first and second metal layers formed on the second surface of the encapsulant, thereby providing a rigid support to the overall structure to prevent warpage and facilitating heat dissipation of the overall structure.

Abstract translation: 半导体封装包括：具有多个电极焊盘的有源表面和与该有源表面相对的无效表面的芯片; 密封剂，其封装所述芯片并且具有相对的第一和第二表面，所述第一表面与所述芯片的有源表面齐平; 以及形成在密封剂的第二表面上的第一和第二金属层，由此为整个结构提供刚性支撑以防止翘曲并促进整体结构的散热。