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    Semiconductor device and fabrication method thereof
    3.
    发明授权
    Semiconductor device and fabrication method thereof 有权
    半导体器件及其制造方法

    公开(公告)号：US08603911B2

    公开(公告)日：2013-12-10

    申请号：US13105338

    申请日：2011-05-11

    申请人： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

    发明人： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

    IPC分类号： H01L21/44 ,  H01L23/12 ,  H01L29/40

    CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

    摘要： A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

    摘要翻译： 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。

    Device of phase locked-loop and the method using the same
    4.
    发明授权
    Device of phase locked-loop and the method using the same 有权
    锁相环装置及其使用方法

    公开(公告)号：US08564343B2

    公开(公告)日：2013-10-22

    申请号：US13422772

    申请日：2012-03-16

    申请人： Hui-Min Huang

    发明人： Hui-Min Huang

    IPC分类号： H03L7/06

    CPC分类号： H03L7/10 ,  H03L7/0891

    摘要： Nowadays, electronic product designs are aimed at saving, due to the trend to reduce energy consumption and carbon output. Ethernet technology has also been aimed specifically at saving energy; IEEE P802.3az standard (Energy Efficient Ethernet, EEE), for Ethernet released by Broadcom is one example. The disclosure turns off the phase-locked loop when the network communication stops, effectively saving the energy consumption of the network chip under the EEE standard. In the case of network reconnection, the disclosure turns on the phase-locked loop to start the network communication through adjusting the current of current source and the parameters of a low pass filter to increase the charging speed for the reference voltage generation of the low pass filter. The disclosure then shortens the start-up time to quickly output the standard output frequency and phase of the phase-locked loop.

    摘要翻译： 目前，电子产品设计的目的是为了节约能源，因为降低能耗和碳输出的趋势。 以太网技术也专门用于节约能源; Broadcom发布的以太网发布的IEEE P802.3az标准（Energy Efficient Ethernet，EEE）就是一个例子。 当网络通信停止时，本公开将关闭锁相环，有效地节省了EEE标准下网络芯片的能耗。 在网络重新连接的情况下，本公开通过调节电流源的电流和低通滤波器的参数来开启锁相环以开始网络通信，以增加用于低通的参考电压产生的充电速度 过滤。 该公开然后缩短启动时间以快速输出锁相环的标准输出频率和相位。

    DEVICE OF PHASE LOCKED-LOOP AND THE METHOD USING THE SAME
    6.
    发明申请
    DEVICE OF PHASE LOCKED-LOOP AND THE METHOD USING THE SAME 有权
    相位锁定装置和使用该锁相环的方法

    公开(公告)号：US20120235719A1

    公开(公告)日：2012-09-20

    申请号：US13422772

    申请日：2012-03-16

    申请人： Hui-Min HUANG

    发明人： Hui-Min HUANG

    IPC分类号： H03L7/10

    CPC分类号： H03L7/10 ,  H03L7/0891

    摘要： Nowadays, electronic product designs are aimed at saving, due to the trend to reduce energy consumption and carbon output. Ethernet technology has also been aimed specifically at saving energy; IEEE P802.3az standard (Energy Efficient Ethernet, EEE), for Ethernet released by Broadcom is one example. The disclosure turns off the phase-locked loop when the network communication stops, effectively saving the energy consumption of the network chip under the EEE standard. In the case of network reconnection, the disclosure turns on the phase-locked loop to start the network communication through adjusting the current of current source and the parameters of a low pass filter to increase the charging speed for the reference voltage generation of the low pass filter. The disclosure then shortens the start-up time to quickly output the standard output frequency and phase of the phase-locked loop.

    摘要翻译： 目前，电子产品设计的目的是为了节约能源，因为降低能耗和碳输出的趋势。 以太网技术也专门用于节约能源; Broadcom发布的以太网发布的IEEE P802.3az标准（Energy Efficient Ethernet，EEE）就是一个例子。 当网络通信停止时，本公开将关闭锁相环，有效地节省了EEE标准下网络芯片的能耗。 在网络重新连接的情况下，本公开通过调节电流源的电流和低通滤波器的参数来开启锁相环以开始网络通信，以增加用于低通的参考电压产生的充电速度 过滤。 该公开然后缩短启动时间以快速输出锁相环的标准输出频率和相位。

    METHOD AND APPARATUS FOR ADJUSTING WAFER WARPAGE
    9.
    发明申请
    METHOD AND APPARATUS FOR ADJUSTING WAFER WARPAGE 有权
    调整波纹的方法和装置

    公开(公告)号：US20130309621A1

    公开(公告)日：2013-11-21

    申请号：US13475790

    申请日：2012-05-18

    申请人： Hui-Min HUANG ,  Chih-Wei LIN ,  Wen-Hsiung LU ,  Ming-Da CHENG ,  Chung-Shi LIU

    发明人： Hui-Min HUANG ,  Chih-Wei LIN ,  Wen-Hsiung LU ,  Ming-Da CHENG ,  Chung-Shi LIU

    IPC分类号： H01L21/687 ,  F27D19/00 ,  F27D5/00

    CPC分类号： H01L21/67288 ,  H01L21/6838

    摘要： A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level.

    摘要翻译： 一种用于调整晶片翘曲的方法，包括提供具有中心部分和边缘部分的晶片，并提供其上具有用于保持晶片的保持区域的保持台。 将晶片放置在保持台上，其中心部分高​​于边缘部分，然后按压到保持区域上，使得晶片通过自吸力被吸引并保持在保持台上。 根据晶片的翘曲量将晶片在预定温度下加热预定时间，以便实现基本上平坦的晶片或预定的晶片级。

    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20120223425A1

    公开(公告)日：2012-09-06

    申请号：US13105338

    申请日：2011-05-11

    申请人： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

    发明人： Hui-Min Huang ,  Chun-Tang Lin ,  Chien-Wei Lee ,  Yen-Ping Wang

    IPC分类号： H01L23/498 ,  H01L21/768

    CPC分类号： H01L23/522 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2224/05552

    摘要： A semiconductor structure includes a chip, a plurality of metal posts disposed in the chip and a buffer layer disposed on the chip. The chip includes a silicon-based layer having opposite first and second surfaces, and a build-up structure formed on the first surface of the silicon-based layer consisting of at least a metal layer and a low-k dielectric layer alternatively stacked on one another. Each of the metal posts is disposed in the silicon-based layer with one end thereof electrically connected with the metal layer while the other end is exposed from the second surface of the silicon-based layer. The buffer layer is disposed on the build-up structure. By positioning the low-k dielectric layer far from the second surface that is used for connecting to an external electronic component, the present invention reduces the overall thermal stress.

    摘要翻译： 半导体结构包括芯片，设置在芯片中的多个金属柱和设置在芯片上的缓冲层。 该芯片包括具有相对的第一和第二表面的硅基层，以及形成在硅基层的第一表面上的堆积结构，该硅基层至少由至少一层金属层和低k电介质层组成， 另一个。 每个金属柱设置在硅基层中，其一端与金属层电连接，而另一端从硅基层的第二表面露出。 缓冲层设置在积聚结构上。 通过将低k电介质层定位成远离用于连接到外部电子部件的第二表面，本发明降低了总的热应力。