公开(公告)号：US06485198B1

公开(公告)日：2002-11-26

申请号：US10021912

申请日：2001-12-12

Applicant: Chung-Tao Chang ,  Bi-Chu Wu ,  Chien Chen ,  Chih-Hsiang Ko

Inventor： Chung-Tao Chang ,  Bi-Chu Wu ,  Chien Chen ,  Chih-Hsiang Ko

IPC: G02B636

CPC classification number: G02B6/4249 ,  G02B6/4204 ,  G02B6/4231 ,  G02B6/4292

Abstract: An optoelectronic transceiver that has integrated optical and electronic components, and can be passively aligned by a flip-chip method and a mechanical method is provided. The optoelectronic transceiver can be constructed by the key components of a circuit board, a silicon sub-mount, at least two IC chips formed on a silicon sub-mount, a microlens array, an optical fiber, and a receptacle for housing the silicon sub-mount, the at least two IC chips, the microlens array and the optical fiber connector in an aligned configuration. The at least two IC chips preferably include a laser diode, a laser diode driver, a photodetector and a photodetector amplifier. The mechanical alignment between a microlens array and a silicon sub-mount is performed by indentations provided in the surfaces of the two parts and the placement of spacer balls in the indentations.

Abstract translation: 提供了具有集成光学和电子部件的光电收发器，并且可以通过倒装芯片方法和机械方法被动地对准。 光电收发器可以由电路板的关键部件，硅子安装座，形成在硅子座上的至少两个IC芯片，微透镜阵列，光纤和用于容纳硅子座的插座构成 以至少两个IC芯片，微透镜阵列和光纤连接器为对齐的结构。 所述至少两个IC芯片优选地包括激光二极管，激光二极管驱动器，光电检测器和光电检测器放大器。 微透镜阵列和硅副安装座之间的机械对准通过设置在两个部分的表面中的凹槽和间隙球在压痕中的放置来进行。

公开(公告)号：US06218726B1

公开(公告)日：2001-04-17

申请号：US09349680

申请日：1999-07-08

Applicant: Chung-Tao Chang ,  Chia-Chung Wang ,  Hsin-Chien Huang

Inventor： Chung-Tao Chang ,  Chia-Chung Wang ,  Hsin-Chien Huang

IPC: H01L23495

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An IC die formed with built-in stress test pattern and a method for forming such pattern are described. The stress test pattern may be formed by first forming a thermal oxide insulation layer on a silicon substrate, then forming a first plurality of diagonally positioned linear metal traces of a first metal, then depositing an electrically insulating material layer on top of the first plurality of diagonally positioned metal traces, and forming a second plurality of L-shaped metal bars of a second metal positioned with the two sides of L parallel to the two sides of a corner region and overlapping the first plurality of metal traces with the electrically insulating material layer therein between. The double metal method for forming the stress test pattern can be easily incorporated into the fabrication process for an IC die without any additional deposition or photolithographic steps. The metal 1 and metal 2 layers may be suitably formed of aluminum or an aluminum alloy, or any other conductive metallic material. The L-shaped metal bars formed by the metal 2 layer should intersect the linear metal traces at a 45° angle with an isolation layer therein between. An electrical resistance between the two metal layers can be determined by a leakage current therein between as a direct indication of the thermo-mechanical stresses, or shear stresses existing between the two metal layers. The present invention stress test pattern can be formed in any size or dimensions as long as one metal layer is formed in linear, diagonal strips while the other metal layer is formed in L-shaped metal bars overlapping the first metal layer.

Abstract translation: 描述了形成有内置应力测试图案的IC模具和用于形成这种图案的方法。 应力测试图案可以通过首先在硅衬底上形成热氧化物绝缘层，然后形成第一金属的第一多个对角定位的线性金属迹线，然后在第一多个第一金属的顶部上沉积电绝缘材料层 对角定位的金属迹线，以及形成第二金属的第二多个L形金属棒，所述第二金属定位成L的两侧平行于拐角区域的两侧，并且与第一多个金属迹线与电绝缘材料层重叠 其间。 用于形成应力测试图案的双金属方法可以容易地并入IC芯片的制造工艺中，而无需任何附加的沉积或光刻步骤。 金属1和金属2层可以适当地由铝或铝合金或任何其它导电金属材料形成。 由金属2层形成的L形金属棒应与其间的隔离层以45°的角度与线性金属迹线相交。 两个金属层之间的电阻可以由其中的泄漏电流确定为热机械应力的直接指示或两个金属层之间存在的剪切应力。 本发明的应力测试图案可以形成为任何尺寸或尺寸，只要一个金属层形成为直线的斜纹条，而另一个金属层形成在与第一金属层重叠的L形金属条中。

公开(公告)号：US5903168A

公开(公告)日：1999-05-11

申请号：US822413

申请日：1997-03-21

Applicant: Jyh-Ren Yang ,  Chung-Tao Chang ,  Ruey-Wen Chien

Inventor： Jyh-Ren Yang ,  Chung-Tao Chang ,  Ruey-Wen Chien

IPC: H03K19/0175

CPC classification number: H03K19/017581 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73269 ,  H01L24/50 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/30107

Abstract: A switchable I/O buffer for multi-chip modules comprising a conventional I/O buffer and a miniaturized I/O buffer. A path switch selects the conventional I/O buffer or the minaturized I/O buffer according to whether the I/O interconnection is for communication off the module or chip-to-chip communication within the module. The miniaturized I/O buffer comprises a single-ended I/O buffer without electrostatic discharge protection. Two layout structures are designed for the switchable I/O buffer. A first layout structure having its path switching control provided by either a cell-programmable method or a mask-programmable method can be used for a multi-chip module or a PWB single package. A second layout structure using a pad-programmable method to provide the path switching control is suitable for a multi-chip module with flip-chip attachment technology. Four different circuit implementations of the switchable I/O buffer are presented. The switchable I/O buffer achieves higher performance with lower power dissipation in that the unnecessary heavy loading and electrostatic discharge protection are eliminated from the interconnection for chip-to-chip communication within the multi-chip module.

Abstract translation: 一种用于多芯片模块的可切换I / O缓冲器，包括常规I / O缓冲器和小型化I / O缓冲器。 路由交换机根据I / O互联是模块间的通信还是模块内的芯片到芯片通信，选择常规的I / O缓冲器或小型I / O缓冲器。 小型化的I / O缓冲器包括没有静电放电保护的单端I / O缓冲器。 为可切换I / O缓冲区设计了两种布局结构。 具有通过单元可编程方法或掩模可编程方法提供的路径切换控制的第一布局结构可以用于多芯片模块或PWB单个封装。 使用焊盘可编程方法提供路径切换控制的第二布局结构适用于具有倒装芯片附接技术的多芯片模块。 提出了可切换I / O缓冲器的四种不同的电路实现方式。 可切换I / O缓冲器实现更高的性能，更低的功耗，因为在多芯片模块内的芯片到芯片通信的互连中消除了不必要的重负载和静电放电保护。

公开(公告)号：US06444561B1

公开(公告)日：2002-09-03

申请号：US09677491

申请日：2000-10-02

Applicant: Chia-Chung Wang ,  Chung-Tao Chang ,  Kuo-Chuan Chen

Inventor： Chia-Chung Wang ,  Chung-Tao Chang ,  Kuo-Chuan Chen

IPC: H01L2144

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3452 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2224/29099 ,  H01L2224/05599

Abstract: A method for forming solder bumps for a flip-chip bonding process wherein the bumps have substantially the same height and structures formed by the method are described. In the method, a pre-processed semiconductor substrate that has a plurality of metal traces formed on a top surface is first provided. At least two solder non-wettable masking strips are then deposited on top of and perpendicular to the plurality of metal traces. The at least two solder non-wettable masking strips are deposited spaced-apart at a predetermined spacing sufficient for forming a bond pad therein-between on the plurality of metal traces. Finally, a solder material is deposited onto the bond pads forming solder bumps which are then reflown into solder balls.

Abstract translation: 描述了用于形成倒装芯片接合工艺的焊料凸块的方法，其中凸块具有基本相同的高度和通过该方法形成的结构。 在该方法中，首先设置具有形成在顶面上的多个金属迹线的预处理半导体基板。 然后将至少两个焊接不可润湿的掩模条沉积在多个金属迹线的顶部并垂直于多个金属迹线。 所述至少两个焊料不可润湿掩模条以足以在其间形成接合焊盘的预定间隔隔开间隔地放置在多个金属迹线之间。 最后，将焊料材料沉积到形成焊料凸块的接合焊盘上，然后将其重新焊接到焊球中。

公开(公告)号：US06647484B1

公开(公告)日：2003-11-11

申请号：US09664839

申请日：2000-09-19

Applicant: Chongjun June Jiang ,  Kan Lu ,  Chung Tao-Chang

Inventor： Chongjun June Jiang ,  Kan Lu ,  Chung Tao-Chang

IPC: G06F1200

CPC classification number: G06F17/16 ,  G06F9/345 ,  G06F9/3552

Abstract: The present invention provides a register-indirect addressing mode using modulo arithmetic to transpose addresses for digital processing systems. The preferred systems and methods permit direct access of column data, which improves matrix computation significantly. The overhead of transpose mode is minimal because it can be implemented, if desired, by sharing hardware and/or software used in circular buffers. Transpose addressing mode also reduces program size and processor power consumed by reducing the sequence of instruction cycles.

Abstract translation: 本发明提供一种使用模数算术来转置数字处理系统的地址的寄存器 - 间接寻址模式。 优选的系统和方法允许直接访问列数据，这显着地改进了矩阵计算。 转置模式的开销是最小的，因为如果需要，可以通过共享在循环缓冲器中使用的硬件和/或软件来实现。 转置寻址模式还通过减少指令周期的顺序来减少程序大小和处理器功耗。

公开(公告)号：US6049216A

公开(公告)日：2000-04-11

申请号：US958116

申请日：1997-10-27

Applicant: Steven J. R. Yang ,  Jane Huei-Chen Chang ,  Chung-Tao Chang ,  Hsiu-Tsang Lee

Inventor： Steven J. R. Yang ,  Jane Huei-Chen Chang ,  Chung-Tao Chang ,  Hsiu-Tsang Lee

IPC: G01R31/28

CPC classification number: G01R31/2863 ,  G01R31/2865

Abstract: Automatic alignment methods for a membrane prober are disclosed. Alignment patterns are designed and manufactured on both a membrane prober and a wafer under test. The patterns are properly designed for acquiring a first set of measurement data that provide relative position information when the prober contacts the wafer. A second set of measurement data can be obtained by a controlled move between the prober and the wafer. The relative position including the translation offset and the rotation angle can be computed by the information derived from the two sets of measurement data. The second set of measurement data may also be acquired by having two alignment pattern pairs that are made to contact in a single touch. More accurate alignment can be achieved by using more pairs of alignment patterns.

Abstract translation: 公开了用于膜探针的自动对准方法。 对准图案是在膜探针和被测晶片上设计和制造的。 这些图案被适当地设计用于获取当探测器接触晶片时提供相对位置信息的第一组测量数据。 可以通过探测器和晶片之间的受控移动来获得第二组测量数据。 可以通过从两组测量数据导出的信息来计算包括平移偏移和旋转角度的相对位置。 第二组测量数据也可以通过使两个对准图案对在单次接触中进行获取。 可以通过使用更多的对齐图案来实现更准确的对准。

公开(公告)号：US06316953B1

公开(公告)日：2001-11-13

申请号：US09364600

申请日：1999-07-30

Applicant: Steven Jyh-Ren Yang ,  Jane Huei-Chen Chan ,  Chung-Tao Chang ,  Hsiu-Tsang Lee

Inventor： Steven Jyh-Ren Yang ,  Jane Huei-Chen Chan ,  Chung-Tao Chang ,  Hsiu-Tsang Lee

IPC: G01R3128

CPC classification number: G01R31/2863 ,  G01R31/2865

Abstract: Automatic alignment methods for a membrane prober are disclosed. Alignment patterns are designed and manufactured on both a membrane prober and a wafer under test. The patterns are properly designed for acquiring a first set of measurement data that provide relative position information when the prober contacts the wafer. A second set of measurement data can be obtained by a controlled move between the prober and the wafer. The relative position including the translation offset and the rotation angle can be computed by the information derived from the two sets of measurement data. The second set of measurement data may also be acquired by having two alignment pattern pairs that are made to contact in a single touch. More accurate aligrnent can be achieved by using more pairs of alignment patterns.

Abstract translation: 公开了用于膜探针的自动对准方法。 对准图案是在膜探针和被测晶片上设计和制造的。 这些图案被适当地设计用于获取当探测器接触晶片时提供相对位置信息的第一组测量数据。 可以通过探测器和晶片之间的受控移动来获得第二组测量数据。 可以通过从两组测量数据导出的信息来计算包括平移偏移和旋转角度的相对位置。 第二组测量数据也可以通过使两个对准图案对在单次接触中进行获取。 可以通过使用更多的对齐图案来实现更精确的浓度。

公开(公告)号：US06433427B1

公开(公告)日：2002-08-13

申请号：US09761487

申请日：2001-01-16

Applicant: Enboa Wu ,  Tsung-Yao Chu ,  Hsin-Chien Huang ,  Chung-Tao Chang

Inventor： Enboa Wu ,  Tsung-Yao Chu ,  Hsin-Chien Huang ,  Chung-Tao Chang

IPC: H01L2940

CPC classification number: H01L24/03 ,  H01L23/3114 ,  H01L23/3192 ,  H01L24/11 ,  H01L2224/02125 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wafer level package that incorporates dual stress buffer layers for achieving I/O pad redistribution and a method for forming the package are disclosed. In the package, a first stress buffer layer and a second stress buffer layer are sequentially deposited on top of an IC die by a method such as spin coating, laminating, screen printing or stencil printing of an elastic material which has a Young's modulus of less than 10 MPa. A suitable thickness for the first and the second stress buffer layer is between about 10 &mgr;m and about 70 &mgr;m. Metal traces are formed on top of the first and the second stress buffer layer for connecting a first plurality of I/O pads and a second plurality of I/O pads to achieve I/O redistribution.

Abstract translation: 公开了一种晶片级封装，其包含用于实现I / O焊盘再分配的双应力缓冲层和形成封装的方法。 在封装中，第一应力缓冲层和第二应力缓冲层通过诸如旋涂，层压，丝网印刷或模板印刷的方法依次沉积在IC管芯的顶部上，弹性材料的杨氏模量较小 超过10MPa。 用于第一和第二应力缓冲层的合适的厚度在约10μm至约70μm之间。 金属迹线形成在用于连接第一多个I / O焊盘和第二多个I / O焊盘的第一和第二应力缓冲层的顶部，以实现I / O再分配。