公开(公告)号：US08004023B2

公开(公告)日：2011-08-23

申请号：US12000504

申请日：2007-12-13

申请人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

发明人： Dae-won Ha ,  Tae-hyun An ,  Min-young Shim

IPC分类号： H01L29/76

CPC分类号： H01L29/94 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/105

摘要： A semiconductor device having a semiconductor substrate including a first region and a second region is provided. The semiconductor device further includes a gate electrode on the first region and having a first sidewall and a second sidewall, a first source region in the first region proximate to the first sidewall, a first drain region in the first region proximate to the second sidewall, an upper electrode on the second region and having a first sidewall and a second sidewall, a second source region in the second region proximate to the first sidewall of the upper electrode, and a second drain region in the second region proximate to the second sidewall of the upper electrode, wherein an impurity doping concentration of the first source region and the first drain region is greater than an impurity doping concentration of the second source region and the second drain region.

摘要翻译： 提供具有包括第一区域和第二区域的半导体衬底的半导体器件。 所述半导体器件还包括位于所述第一区域上并具有第一侧壁和第二侧壁的栅电极，所述第一区域中靠近所述第一侧壁的第一源极区域，所述第一区域中靠近所述第二侧壁的第一漏极区域， 在第二区域上的上电极，具有第一侧壁和第二侧壁，第二区域中靠近上电极的第一侧壁的第二区域，以及靠近第二侧壁的第二区域中的第二漏极区域 所述上电极，其中所述第一源极区域和所述第一漏极区域的杂质掺杂浓度大于所述第二源极区域和所述第二漏极区域的杂质掺杂浓度。

公开(公告)号：US20110084361A1

公开(公告)日：2011-04-14

申请号：US12973253

申请日：2010-12-20

申请人： Dae-Won Ha ,  Sang-Yoon Kim

发明人： Dae-Won Ha ,  Sang-Yoon Kim

IPC分类号： H01L27/06

CPC分类号： H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233

摘要： A semiconductor device having a resistor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a first circuit region and a second circuit region. A lower interlayer insulating layer is provided over the semiconductor substrate. A first hole passing through the lower interlayer insulating layer in the first circuit region and a second hole passing through the lower interlayer insulating layer in the second circuit region are provided. A first semiconductor pattern and a second semiconductor pattern are sequentially stacked in the first hole. A first resistor having the same crystalline structure as the second semiconductor pattern is provided in the second hole.

摘要翻译： 提供了具有电阻器的半导体器件及其制造方法。 半导体器件包括具有第一电路区域和第二电路区域的半导体衬底。 在半导体衬底上设置下层层间绝缘层。 提供穿过第一电路区域中的下层间绝缘层的第一孔和穿过第二电路区域中的下层间绝缘层的第二孔。 第一半导体图案和第二半导体图案依次堆叠在第一孔中。 具有与第二半导体图案相同的晶体结构的第一电阻器设置在第二孔中。

公开(公告)号：US20110044093A1

公开(公告)日：2011-02-24

申请号：US12917175

申请日：2010-11-01

申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

公开(公告)号：US07843718B2

公开(公告)日：2010-11-30

申请号：US12178962

申请日：2008-07-24

申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

IPC分类号： G11C11/00 ,  G11C5/06 ,  G11C11/15

CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

公开(公告)号：US20090201721A1

公开(公告)日：2009-08-13

申请号：US12320963

申请日：2009-02-10

申请人： Dae-Won Ha ,  Jung-Huyk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

发明人： Dae-Won Ha ,  Jung-Huyk Lee ,  Gi-Tae Jeong ,  Hyeong-Jun Kim

IPC分类号： G11C11/00 ,  G11C11/416 ,  G11C5/14

CPC分类号： G11C13/0069 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0033 ,  G11C14/00 ,  G11C16/3431 ,  G11C29/028 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device and a write method thereof allow writing of both volatile and non-volatile data on the phase change memory device. The phase change memory device may be written by setting a write mode as one of a volatile write mode and a non-volatile write mode, and writing data as volatile or non-volatile by applying a write pulse corresponding to the write mode, wherein, when power is not supplied to the phase change memory device, the non-volatile data is retained and the volatile data is not retained.

摘要翻译： 相变存储器件及其写入方法允许在相变存储器件上写入易失性和非易失性数据。 可以通过将写入模式设置为易失性写入模式和非易失性写入模式之一来写入相变存储器件，并且通过施加与写入模式对应的写入脉冲将数据写入作为易失性或非易失性， 当不向相变存储器件供电时，保持非易失性数据并且不保留易失性数据。

公开(公告)号：US07557403B2

公开(公告)日：2009-07-07

申请号：US11379432

申请日：2006-04-20

申请人： Dae-Won Ha

发明人： Dae-Won Ha

IPC分类号： H01L29/788

CPC分类号： H01L29/4925 ,  H01L21/266 ,  H01L29/6659 ,  H01L29/66795 ,  H01L29/7851

摘要： Double gate transistors having at least two polysilicon patterns on a thin body used as an active region and methods of forming the same are provided. Embodiments of the transistors and methods provided are capable of enhancing current drivability of a semiconductor memory device using polysilicon patterns having different impurity concentrations from each other. In some embodiments an active region is protruded from a semiconductor substrate, an impurity diffusion region is formed in the active region, and a gate insulating pattern and a gate pattern are sequentially stacked on the active region. In these embodiments, the gate pattern may include polysilicon patterns having different impurity concentrations from each other.

摘要翻译： 提供了在用作活性区域的薄体上具有至少两个多晶硅图案的双栅极晶体管及其形成方法。 提供的晶体管和方法的实施例能够使用具有彼此不同杂质浓度的多晶硅图案来提高半导体存储器件的电流驱动能力。 在一些实施例中，有源区从半导体衬底突出，在有源区中形成杂质扩散区，并且栅极绝缘图案和栅极图案依次层叠在有源区上。 在这些实施例中，栅极图案可以包括彼此具有不同杂质浓度的多晶硅图案。

公开(公告)号：US20090034319A1

公开(公告)日：2009-02-05

申请号：US12120583

申请日：2008-05-14

申请人： Dae-Won HA ,  Gi-Tae JEONG

发明人： Dae-Won HA ,  Gi-Tae JEONG

IPC分类号： H01L27/26 ,  G11C11/34

CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

摘要翻译： 相变存储器件包括沿着半导体衬底上的方向延伸的字线。 低浓度半导体图案设置在字线上。 节点电极设置在低浓度半导体图案上。 肖特基二极管设置在低浓度半导体图案和节点电极之间。 相变电阻器设置在节点电极上。

公开(公告)号：US20090027955A1

公开(公告)日：2009-01-29

申请号：US12178962

申请日：2008-07-24

申请人： Gwan-Hyeob Koh ,  Dae-Won Ha

发明人： Gwan-Hyeob Koh ,  Dae-Won Ha

IPC分类号： G11C11/00 ,  H01L47/00 ,  H01L29/82 ,  H01L21/00

CPC分类号： G11C13/003 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/147

摘要： A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.

摘要翻译： 非易失性存储器件包括衬底，衬底上的绝缘层和堆叠在绝缘层中的多个串联连接的电阻性存储器单元，使得多个电阻存储器单元中的第一个位于衬底上，下一个 多个电阻存储器单元中的一个位于多个电阻存储器单元中的第一个上，以限定NAND型电阻存储单元串。 绝缘层上的位线电连接到多个电阻存储单元中的最后一个。 多个电阻式存储单元中的至少一个可以包括开关器件和包括与开关器件并联连接的可变电阻器的数据存储元件。 还讨论了相关设备和制造方法。

公开(公告)号：US20080036016A1

公开(公告)日：2008-02-14

申请号：US11871876

申请日：2007-10-12

申请人： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

发明人： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

IPC分类号： H01L29/78

CPC分类号： H01L21/823437 ,  H01L21/823481

摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

公开(公告)号：US20070020862A1

公开(公告)日：2007-01-25

申请号：US11421171

申请日：2006-05-31

申请人： Dae-Won HA

发明人： Dae-Won HA

IPC分类号： H01L21/336

CPC分类号： H01L21/76224 ,  H01L29/78

摘要： In an embodiment, a semiconductor device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate of the field region to define the active region, and has a protrusion higher than a surface of the semiconductor substrate. A gate pattern is formed on and across the semiconductor substrate of the active region, and has a top surface disposed on substantially the same plane as a top surface of the trench isolation layer. A gate line is formed, which is self-aligned with the gate pattern to cover the gate pattern and extends over the trench isolation layer. A reduction in an effective channel length of the device due to excess trapped electrons is prevented.

摘要翻译： 在一个实施例中，半导体器件包括具有有源区和与有源区接触的场区的半导体衬底。 沟道隔离层形成在场区域的半导体衬底内以限定有源区，并且具有高于半导体衬底的表面的突起。 栅极图案形成在有源区的半导体衬底上并跨越半导体衬底，并且具有设置在与沟槽隔离层的顶表面基本相同的平面上的顶表面。 形成栅极线，其与栅极图案自对准以覆盖栅极图案并且在沟槽隔离层上延伸。 防止由于过量捕获的电子而导致器件的有效沟道长度的减小。