公开(公告)号：US20160197188A1

公开(公告)日：2016-07-07

申请号：US15071502

申请日：2016-03-16

申请人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

发明人： Dong-Suk Shin ,  Myung-Sun Kim ,  Seong-Jin Nam ,  Pan-Kwi Park ,  Hoi-Sung Chung ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/51 ,  H01L27/11 ,  H01L29/45 ,  H01L27/088 ,  H01L29/08 ,  H01L29/165

CPC分类号： H01L27/1104 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28247 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/088 ,  H01L27/1116 ,  H01L29/0847 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/45 ,  H01L29/513 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7827 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78696

摘要： In a semiconductor device, a first active region has a first Σ-shape, and the second active region has a second Σ-shape. When a line that is perpendicular to the substrate and passes a side surface of a first gate electrode in the first region is defined as a first vertical line, when a line that is perpendicular to the substrate and passes a side surface of a second gate electrode in the second region is defined as a second vertical line, when a shortest distance between the first vertical line and the first trench is defined as a first horizontal distance, and when a shortest distance between the second vertical line and the second trench is defined as a second horizontal distance, a difference between the first horizontal distance and the second horizontal distance is equal to or less than 1 nm.

公开(公告)号：US20160079424A1

公开(公告)日：2016-03-17

申请号：US14951932

申请日：2015-11-25

申请人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

发明人： Dong-Suk SHIN ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim ,  Nae-In Lee

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/167

CPC分类号： H01L29/7848 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L29/045 ,  H01L29/0603 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

摘要： Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.

公开(公告)号：US08742806B2

公开(公告)日：2014-06-03

申请号：US13442426

申请日：2012-04-09

申请人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

发明人： Won Joo Yun ,  Hyun Woo Lee ,  Dong Suk Shin

IPC分类号： H03L7/06 ,  H03L7/081

CPC分类号： H03L7/0812

摘要： A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

摘要翻译： 一种控制功率控制电路的方法包括：当延迟锁定环路（DLL）电路的延迟锁定操作完成时，使能电源切断信号，在预定时间内禁用电源切断信号，并检测参考时钟 以及反馈时钟，基于检测结果来重新确定是否启用电源切断信号。

公开(公告)号：US08637373B2

公开(公告)日：2014-01-28

申请号：US13410475

申请日：2012-03-02

申请人： Hoi-Sung Chung ,  Dong-Suk Shin ,  Dong-Hyuk Kim ,  Myung-Sun Kim

发明人： Hoi-Sung Chung ,  Dong-Suk Shin ,  Dong-Hyuk Kim ,  Myung-Sun Kim

IPC分类号： H01L21/336

CPC分类号： H01L21/823807 ,  H01L21/30608 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

摘要： In a method of manufacturing a transistor, a gate structure is formed on a substrate including silicon. An upper portion of the substrate adjacent to the gate structure is etched to form a first recess in the substrate. A preliminary first epitaxial layer including silicon-germanium is formed in the first recess. An upper portion of the preliminary first epitaxial layer is etched to form a second recess on the preliminary first epitaxial layer. In addition, a portion of the preliminary first epitaxial layer adjacent to the second recess is etched to thereby transform the preliminary first epitaxial layer into a first epitaxial layer. A second epitaxial layer including silicon-germanium is formed in the second recess located on the first epitaxial layer.

摘要翻译： 在制造晶体管的方法中，在包括硅的衬底上形成栅极结构。 蚀刻与栅极结构相邻的衬底的上部，以在衬底中形成第一凹部。 在第一凹部中形成包括硅 - 锗的初步的第一外延层。 蚀刻初步第一外延层的上部以在初步第一外延层上形成第二凹槽。 此外，蚀刻与第二凹槽相邻的初步第一外延层的一部分，从而将初步第一外延层转变为第一外延层。 在位于第一外延层上的第二凹槽中形成包括硅 - 锗的第二外延层。

公开(公告)号：US08624629B2

公开(公告)日：2014-01-07

申请号：US13528148

申请日：2012-06-20

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： G01R25/00

CPC分类号： H03L7/089 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/0028

摘要： A delay value control circuit of a phase difference quantization circuit, wherein the phase difference quantization circuit has first to Nth (N is an integer equal to or greater than 2) delay units with binary weights. The delay value control circuit includes a replica delay unit replicating an Ath (2≦A≦N) delay unit; and a delay control unit configured to compare a phase of a first output signal generated from delaying an input signal with an A−1th delay unit and a phase of a second output signal generated from delaying the input signal with the Ath delay unit and the replica delay unit and configured to control a delay value of the Ath delay unit using a comparison result.

摘要翻译： 一种相位差量化电路的延迟值控制电路，其中相位差量化电路具有二进制权重的第一至第N（N是等于或大于2的整数）延迟单元。 延迟值控制电路包括复制Ath（2 @ A @ N）延迟单元的复制延迟单元; 以及延迟控制单元，被配置为比较从延迟输入信号产生的第一输出信号与第一延迟单元的相位和从延迟输入信号而产生的第二输出信号的相位与Ath延迟单元和副本 延迟单元，并且被配置为使用比较结果来控制Ath延迟单元的延迟值。

公开(公告)号：US08390353B2

公开(公告)日：2013-03-05

申请号：US13332964

申请日：2011-12-21

申请人： Dong Suk Shin ,  Kwang Jin Na

发明人： Dong Suk Shin ,  Kwang Jin Na

IPC分类号： H03K3/017

CPC分类号： H03K5/04

摘要： A duty cycle correction circuit includes a duty correction block configured to generate a first pre-corrected signal and a second pre-corrected signal in response to a duty code and an input signal; a duty-corrected signal generation block configured to generate a duty-corrected signal in response to a first select signal, a second select signal, the first pre-corrected signal and the second pre-corrected signal; and a control block configured to generate the duty code, the first select signal and the second select signal in response to the duty-corrected signal and the input signal.

摘要翻译： 占空比校正电路包括占空比校正块，其被配置为响应于占空比代码和输入信号产生第一预校正信号和第二预校正信号; 配置为响应于第一选择信号，第二选择信号，第一预校正信号和第二预校正信号产生占空比校正信号的占空比校正信号产生块; 以及控制块，被配置为响应于占空比校正信号和输入信号而产生占空比代码，第一选择信号和第二选择信号。

公开(公告)号：US08344771B2

公开(公告)日：2013-01-01

申请号：US12938081

申请日：2010-11-02

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： H03L7/06

CPC分类号： H03L7/0818

摘要： A delay locked loop (DLL) of a semiconductor integrated circuit includes a first delay line configured to variably delay a source clock signal and output a locked clock signal, a phase comparator configured to compare the phase of the source clock signal with the phase of a feedback clock signal, a second delay line configured to variably delay the locked clock signal, a first delay controller configured to control the first delay time of the first delay line, a second delay controller configured to control the minimum delay time of the second delay line, and an operation mode controller configured to control the first and second delay controllers in response to an output signal of the phase comparator, and switch operation modes of the first and second delay controllers depending on locking state of the delay lines.

摘要翻译： 半导体集成电路的延迟锁定环（DLL）包括：第一延迟线，被配置为可变地延迟源时钟信号并输出​​锁定的时钟信号;相位比较器，被配置为将源时钟信号的相位与 反馈时钟信号，被配置为可变延迟锁定的时钟信号的第二延迟线;配置成控制第一延迟线的第一延迟时间的第一延迟控制器，被配置为控制第二延迟线的最小延迟时间的第二延迟控制器 以及操作模式控制器，被配置为响应于相位比较器的输出信号来控制第一和第二延迟控制器，以及根据延迟线的锁定状态的第一和第二延迟控制器的切换操作模式。

公开(公告)号：US20120081161A1

公开(公告)日：2012-04-05

申请号：US12983177

申请日：2010-12-31

申请人： Dong Suk SHIN

发明人： Dong Suk SHIN

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  G11C8/04 ,  H03L7/0812

摘要： A synchronization circuit includes a first loop circuit configured to set an initial delay time by using first initial delay information and generate a first delay signal by changing a delay time of a first input signal, a second loop circuit configured to set the initial delay time by using second initial delay information and generate a second delay signal by changing a delay time of a second input signal, a duty cycle correction unit configured to correct a duty cycle of the first delay signal by using the second delay signal, and an initial delay monitoring circuit configured to generate the first initial delay information and the second initial delay information in response to an internal delay signal of the first loop circuit and the first input signal.

摘要翻译： 同步电路包括第一环路电路，其被配置为通过使用第一初始延迟信息来设置初始延迟时间，并且通过改变第一输入信号的延迟时间来产生第一延迟信号，第二环路电路被配置为将初始延迟时间设置为 使用第二初始延迟信息并通过改变第二输入信号的延迟时间来产生第二延迟信号;占空比校正单元，被配置为通过使用第二延迟信号来校正第一延迟信号的占空比，以及初始延迟监视 电路，被配置为响应于第一环路电路和第一输入信号的内部延迟信号产生第一初始延迟信息和第二初始延迟信息。

公开(公告)号：US20110306198A1

公开(公告)日：2011-12-15

申请号：US13157615

申请日：2011-06-10

申请人： Yong-Kuk Jeong ,  Dong-Suk Shin ,  Jong-Hun Kim ,  Hyun-Kwan Yu ,  Ki-eun Kim

发明人： Yong-Kuk Jeong ,  Dong-Suk Shin ,  Jong-Hun Kim ,  Hyun-Kwan Yu ,  Ki-eun Kim

IPC分类号： H01L21/28

CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7843

摘要： A method of fabricating a semiconductor integrated circuit device includes forming a gate pattern on a semiconductor substrate, the gate pattern having a gate insulation film and a gate electrode. A spacer is formed on sidewalls of the gate pattern. A silicide layer is formed by a silicide process on at least one portion of the semiconductor substrate exposed by the gate pattern and the spacer, the silicide layer being formed using a silicide process. A stress buffer layer is formed on a resultant structure having the silicide layer. A stress film is formed on the stress buffer layer.

摘要翻译： 一种制造半导体集成电路器件的方法包括在半导体衬底上形成栅极图案，栅极图案具有栅极绝缘膜和栅电极。 在栅极图案的侧壁上形成间隔物。 硅化物层通过硅化物工艺在由栅极图案和间隔物暴露的半导体衬底的至少一部分上形成，硅化物层使用硅化物工艺形成。 在具有硅化物层的所得结构上形成应力缓冲层。 在应力缓冲层上形成应力膜。

公开(公告)号：US20110291725A1

公开(公告)日：2011-12-01

申请号：US12832092

申请日：2010-07-08

申请人： Dong-Suk Shin

发明人： Dong-Suk Shin

IPC分类号： H03K3/017

CPC分类号： G11C7/22 ,  G11C7/222 ,  H03K5/1565 ,  H03K9/08

摘要： A duty cycle correction circuit includes a duty adjustment circuit configured to generate an output clock by adjusting a duty cycle of an input clock in response to a duty adjustment code, a duty detection circuit configured to measure a difference between a width of a high pulse and a width of a low pulse of the output clock at each update period, and generate a duty detection code corresponding to the measured value, an accumulation circuit configured to generate the duty adjustment code by accumulating a value of the duty detection code outputted at each update period, and a toggling number adjustment circuit configured to adjust a toggling number of the output clock, which adjustment determines the update period, according to a frequency of the output clock.

摘要翻译： 占空比校正电路包括占空比调整电路，其被配置为通过响应于占空比调整代码调整输入时钟的占空比来产生输出时钟;占空比检测电路，被配置为测量高脉冲宽度与 在每个更新周期的输出时钟的低脉冲的宽度，并且生成与测量值相对应的占空比检测码;累加电路，被配置为通过累加在每次更新时输出的占空比检测码的值来生成占空比调整码 周期，以及切换数量调整电路，被配置为根据输出时钟的频率来调整输出时钟的切换次数，该调整确定更新周期。