公开(公告)号：US20130069108A1

公开(公告)日：2013-03-21

申请号：US13313713

申请日：2011-12-07

申请人： Young Ki LEE ,  Dong Soo SEO ,  Kwang Soo KIM ,  Young Hoon KWAK

发明人： Young Ki LEE ,  Dong Soo SEO ,  Kwang Soo KIM ,  Young Hoon KWAK

IPC分类号： H01L29/739

CPC分类号： H01L23/4824 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a power semiconductor module including: a circuit board having gate, emitter, and collector patterns formed thereon; a first semiconductor chip mounted on the circuit board, having gate and emitter terminals each formed on one surface thereof, and having a collector terminal formed on the other surface thereof; a second semiconductor chip mounted on the first semiconductor chip, having a cathode terminal formed on one surface thereof, and having an anode terminal formed on the other surface thereof; a first conductive connection member having one end disposed between the collector terminal of the first semiconductor chip and the cathode terminal of the second semiconductor chip and the other end contacting the collector pattern of the circuit board; and a second conductive connection member having one end contacting the anode terminal of the second semiconductor chip and the other end contacting the emitter pattern of the circuit board.

摘要翻译： 本文公开了一种功率半导体模块，包括：电路板，其上形成有栅极，发射极和集电极图案; 安装在所述电路板上的第一半导体芯片，在其一个表面上形成有栅极和发射极端子，并且在其另一个表面上形成集电极端子; 安装在所述第一半导体芯片上的第二半导体芯片，具有在其一个表面上形成的阴极端子，并且在其另一个表面上形成阳极端子; 第一导电连接构件，其一端设置在第一半导体芯片的集电极端子和第二半导体芯片的阴极端子之间，另一端接触电路板的集电体图案; 以及第二导电连接构件，其一端接触第二半导体芯片的阳极端子，另一端接触电路板的发射极图案。

公开(公告)号：US08796730B2

公开(公告)日：2014-08-05

申请号：US13313713

申请日：2011-12-07

申请人： Young Ki Lee ,  Dong Soo Seo ,  Kwang Soo Kim ,  Young Hoon Kwak

发明人： Young Ki Lee ,  Dong Soo Seo ,  Kwang Soo Kim ,  Young Hoon Kwak

IPC分类号： H01L29/739

CPC分类号： H01L23/4824 ,  H01L29/7393 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed herein is a power semiconductor module including: a circuit board having gate, emitter, and collector patterns formed thereon; a first semiconductor chip mounted on the circuit board, having gate and emitter terminals each formed on one surface thereof, and having a collector terminal formed on the other surface thereof; a second semiconductor chip mounted on the first semiconductor chip, having a cathode terminal formed on one surface thereof, and having an anode terminal formed on the other surface thereof; a first conductive connection member having one end disposed between the collector terminal of the first semiconductor chip and the cathode terminal of the second semiconductor chip and the other end contacting the collector pattern of the circuit board; and a second conductive connection member having one end contacting the anode terminal of the second semiconductor chip and the other end contacting the emitter pattern of the circuit board.

摘要翻译： 本文公开了一种功率半导体模块，包括：电路板，其上形成有栅极，发射极和集电极图案; 安装在所述电路板上的第一半导体芯片，在其一个表面上形成有栅极和发射极端子，并且在其另一个表面上形成集电极端子; 安装在所述第一半导体芯片上的第二半导体芯片，具有在其一个表面上形成的阴极端子，并且在其另一个表面上形成阳极端子; 第一导电连接构件，其一端设置在第一半导体芯片的集电极端子和第二半导体芯片的阴极端子之间，另一端接触电路板的集电体图案; 以及第二导电连接构件，其一端接触第二半导体芯片的阳极端子，另一端接触电路板的发射极图案。

公开(公告)号：US20070164431A1

公开(公告)日：2007-07-19

申请号：US11549933

申请日：2006-10-16

申请人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

发明人： In Young LEE ,  Hyun-Soo CHUNG ,  Dong-Ho LEE ,  Sung-Min SIM ,  Dong-Soo SEO ,  Seung-Kwan RYU ,  Myeong-Soon PARK

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L23/3114 ,  H01L23/5222 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/02313 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/30105 ,  H01L2924/351 ,  H01L2924/00

摘要： A wafer level chip scale package capable of reducing parasitic capacitances between a rerouting and the metal wiring of a wafer, and a method for manufacturing the same are provided. An embodiment of the wafer level chip scale package includes a wafer arranged with a plurality of bonding pads and an insulating member formed on the wafer so that the bonding pads are exposed. A rerouting is further formed on the insulating member in contact with the exposed bonding pads and an external connecting terminal is electrically connected to a portion of the rerouting. Here, the insulating member overlapping the rerouting is provided with a plurality of spaces in which air is trapped.

摘要翻译： 提供能够降低重新布线和晶片的金属布线之间的寄生电容的晶片级芯片级封装及其制造方法。 晶片级芯片级封装的实施例包括具有多个接合焊盘的晶片和形成在晶片上的绝缘部件，使得焊盘露出。 在与暴露的接合焊盘接触的绝缘构件上进一步形成再路由，并且外部连接端子电连接到重新布线的一部分。 这里，与重新路由重叠的绝缘构件设置有空气被捕获的多个空间。

公开(公告)号：US20130161737A1

公开(公告)日：2013-06-27

申请号：US13620518

申请日：2012-09-14

申请人： Jaehoon PARK ,  Dong Soo SEO

发明人： Jaehoon PARK ,  Dong Soo SEO

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7803 ,  H01L29/7827

摘要： There are provided a semiconductor device and a method of manufacturing the same, capable of removing a shoot-through phenomenon by forming capacitance between an electrode and a lateral surface of a protrusion region of a gate and increasing a gate-source capacitance. The semiconductor device may include: a semiconductor body having a predetermined volume; a source formed on an upper surface of the semiconductor body; a gate formed in a groove of the semiconductor body and having a protrusion region protruded upwardly of the upper surface of the semiconductor body, the groove having a predetermined depth and the protrusion region having a protrusion height altered depending on a level of capacitance to be set; and an electrode electrically connected to the source to form capacitance together with a lateral surface of the protrusion region of the gate.

摘要翻译： 提供了一种半导体器件及其制造方法，其能够通过在电极和栅极的突出区域的侧表面之间形成电容并增加栅极 - 源极电容来消除直通现象。 半导体器件可以包括：具有预定体积的半导体本体; 形成在所述半导体本体的上表面上的源极; 形成在半导体本体的沟槽中并具有从半导体本体的上表面向上突出的突起区域的栅极，该沟槽具有预定深度，并且突起高度根据要设置的电容水平而改变 ; 以及电连接到源极以与栅极的突出区域的侧表面一起形成电容的电极。

公开(公告)号：US5849607A

公开(公告)日：1998-12-15

申请号：US598849

申请日：1996-02-09

申请人： Dong Soo Seo ,  Wan Gyun Choi ,  Young Jae Song ,  Jae Myung Park

发明人： Dong Soo Seo ,  Wan Gyun Choi ,  Young Jae Song ,  Jae Myung Park

IPC分类号： H01L21/603 ,  H01L21/56 ,  H01L21/60

CPC分类号： H01L24/80 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01077 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/14 ,  H01L2924/181

摘要： A method for manufacturing of a lead-on-chip type semiconductor chip package is disclosed, which comprises the steps of coating a liquid polyimide coating material on the bonding faces of at least one of the inner leads and the bus bars of the lead frame and the semiconductor chip, attaching the semiconductor chip by using the cured liquid polyimide coating material as an attaching medium, and forming a package body for wrapping and protecting the semiconductor chip and bonding wires. Since the liquid polyimide coating material protects the wafer from which the chips are obtained and also serves as a bonding agent for the semiconductor chip at the same time, the semiconductor chip package according to the present invention can be protected from damage, such as by air bubbles, which are generated at the interface of the conventional polyimide tape, and by separation and expansion of adhesives. Consequently, the method is applicable to a semiconductor chip package having a thickness that is thinner than that of conventional semiconductor chip package.

摘要翻译： 公开了一种制造片上型芯片型半导体芯片封装的方法，其包括以下步骤：在引线框架的内引线和母线的至少一个的接合面上涂布液体聚酰亚胺涂层材料，以及 半导体芯片，通过使用固化的液体聚酰亚胺涂层材料作为附着介质附着半导体芯片，以及形成用于包覆和保护半导体芯片和接合线的封装体。 由于液体聚酰亚胺涂层材料保护了获得芯片的晶片，并且同时用作半导体芯片的粘结剂，因此可以保护根据本发明的半导体芯片封装件不受诸如空气的损坏 在常规聚酰亚胺胶带的界面处产生的气泡，以及粘合剂的分离和膨胀。 因此，该方法适用于厚度比现有的半导体芯片封装薄的半导体芯片封装。