Plastic deformation magnesium alloy having excellent thermal conductivity and flame retardancy, and preparation method

    公开(公告)号:US10767248B2

    公开(公告)日:2020-09-08

    申请号:US15553688

    申请日:2016-02-24

    申请人: In-Young Lee

    IPC分类号: C22C23/04 C22C1/02 C22C23/06

    摘要: Disclosed is a magnesium alloy that has high thermal conductivity and flame retardancy and facilitates plastic working, wherein magnesium is added with 0.5 to 5 wt % of zinc (Zn) and 0.3 to 2.0 wt % of at least one of yttrium (Y) and mischmetal, with, as necessary, 1.0 wt % or less of at least one selected from among calcium (Ca), silicon (Si), manganese (Mn) and tin (Sn), the total amount of alloy elements being 2.5 to 6 wt %. A method of manufacturing the same is also provided, including preparing a magnesium-zinc alloy melt in a melting furnace, adding high-melting-point elements in the form of a master alloy and melting them, and performing mechanical stirring during cooling of a cast material in a continuous casting mold containing the magnesium alloy melt, thus producing a magnesium alloy cast material having low segregation, after which a chill is removed from the cast material or diffusion annealing is performed, followed by molding through a tempering process such as rolling, extrusion or forging. This magnesium alloy is improved in ductility by the action of alloy elements for inhibiting the formation of lamella precipitates due to a low-melting-point eutectic phase in a magnesium matrix structure, can be extruded even at a pressure of 1,000 kgf/cm2 or less due to the increased plasticity thereof, and can exhibit thermal conductivity of 100 W/m·K or more and flame retardancy satisfying the requirements for aircraft materials and is thus suitable for use in fields requiring fire safety, thereby realizing wide application thereof as a heat sink or a structural material for portable appliances, vehicles and aircraft components and contributing to weight reduction.

    SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING
    2.
    发明申请
    SEMICONDUCTOR PACKAGE INCLUDING SEMICONDUCTOR CHIP WITH THROUGH OPENING 有权
    半导体封装,包括通过开放的半导体芯片

    公开(公告)号:US20130105988A1

    公开(公告)日:2013-05-02

    申请号:US13533473

    申请日:2012-06-26

    IPC分类号: H01L23/48

    摘要: A semiconductor package comprises a substrate having a first opening formed therethrough, a first semiconductor chip stacked on the substrate in a flip chip manner and having a second opening formed therethrough, a second semiconductor chip stacked on the first semiconductor chip in a flip chip manner and having a third opening formed therethrough, and a molding material covering the first semiconductor chip and the second semiconductor chip and filling up a space between the substrate and the first semiconductor chip, a space between the first semiconductor chip and the second semiconductor chip, and filling each of the first opening, the second opening, and the third opening.

    摘要翻译: 半导体封装包括具有通过其形成的第一开口的衬底,以倒装芯片方式堆叠在衬底上并具有穿过其中的第二开口的第一半导体芯片,以倒装芯片方式堆叠在第一半导体芯片上的第二半导体芯片,以及 具有通过其形成的第三开口,以及覆盖所述第一半导体芯片和所述第二半导体芯片并填充所述基板和所述第一半导体芯片之间的空间的模塑材料,所述第一半导体芯片和所述第二半导体芯片之间的空间,以及填充 第一开口,第二开口和第三开口中的每一个。

    Switch, negative resistance cell, and differential voltage controlled oscillator using the same
    4.
    发明授权
    Switch, negative resistance cell, and differential voltage controlled oscillator using the same 失效
    开关,负极电阻和差分电压控制振荡器使用

    公开(公告)号:US07741922B2

    公开(公告)日:2010-06-22

    申请号:US12257920

    申请日:2008-10-24

    CPC分类号: H03B5/1212 H03B5/1228

    摘要: The present invention relates to a switch, a negative resistance cell, and a differential voltage controlled oscillator using the same. The present invention includes a first signal line provided in a first direction, a second signal line provided in parallel with the first signal line, and first to fourth gate electrodes, first to third source electrodes, and first to fourth drain electrodes formed between the first signal line and the second signal line, and provides a switch having electrodes in the order of the first gate electrode, the first drain electrode, the second gate electrode, the first source electrode, the third gate electrode, the second drain electrode, the fourth gate electrode, the second source electrode, the fifth gate electrode, the third drain electrode, the sixth gate electrode, the third source electrode, the seventh gate electrode, the fourth drain electrode, and the eighth gate electrode. According to the present invention, a differential voltage controlled oscillator for RF oscillation operation in the broadband area is realized by minimizing generation of parasitic components.

    摘要翻译: 本发明涉及一种开关,负电阻单元和使用该开关的差分电压控制振荡器。 本发明包括沿第一方向设置的第一信号线,与第一信号线并联设置的第二信号线,以及第一至第四栅电极,第一至第三源电极和形成在第一信号线之间的第一至第四漏极 信号线和第二信号线,并且提供具有按照第一栅电极,第一漏电极,第二栅电极,第一源电极,第三栅电极,第二漏电极,第四电极的顺序的电极的开关 第二栅极电极,第二源极电极,第五栅极电极,第三漏极电极,第六栅极电极,第三源极电极,第七栅极电极,第四漏极电极和第八栅极电极。 根据本发明,通过最小化寄生分量的产生来实现在宽带区域中用于RF振荡操作的差分压控振荡器。

    Semiconductor device having through vias
    6.
    发明授权
    Semiconductor device having through vias 有权
    具有通孔的半导体器件

    公开(公告)号:US07602047B2

    公开(公告)日:2009-10-13

    申请号:US11979562

    申请日:2007-11-06

    IPC分类号: H01L29/40

    摘要: A method of fabricating a semiconductor device is provided. The method may include forming an insulating layer on a wafer. The wafer may have an active surface and an inactive surface which face each other, and the insulating layer may be formed on the active surface. A pad may be formed on the insulating layer, and a first hole may be formed in the insulating layer. A first hole insulating layer may then be formed on an inner wall of the first hole. A second hole may be formed under the first hole. The second hole may be formed to extend from the first hole into the wafer. A second hole insulating layer may be formed on an inner wall of the second hole. The semiconductor device fabricated according to the method may also be provided.

    摘要翻译: 提供一种制造半导体器件的方法。 该方法可以包括在晶片上形成绝缘层。 晶片可以具有彼此面对的有源表面和非活性表面,并且绝缘层可以形成在有源表面上。 可以在绝缘层上形成焊盘,并且可以在绝缘层中形成第一孔。 然后可以在第一孔的内壁上形成第一孔绝缘层。 可以在第一孔下方形成第二孔。 第二孔可以形成为从第一孔延伸到晶片。 第二孔绝缘层可以形成在第二孔的内壁上。 还可以提供根据该方法制造的半导体器件。

    SWITCH, NEGATIVE RESISTANCE CELL, AND DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR USING THE SAME
    7.
    发明申请
    SWITCH, NEGATIVE RESISTANCE CELL, AND DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATOR USING THE SAME 失效
    开关,负极电阻和差分电压控制振荡器

    公开(公告)号:US20090108946A1

    公开(公告)日:2009-04-30

    申请号:US12257920

    申请日:2008-10-24

    IPC分类号: H03L5/00

    CPC分类号: H03B5/1212 H03B5/1228

    摘要: The present invention relates to a switch, a negative resistance cell, and a differential voltage controlled oscillator using the same. The present invention includes a first signal line provided in a first direction, a second signal line provided in parallel with the first signal line, and first to fourth gate electrodes, first to third source electrodes, and first to fourth drain electrodes formed between the first signal line and the second signal line, and provides a switch having electrodes in the order of the first gate electrode, the first drain electrode, the second gate electrode, the first source electrode, the third gate electrode, the second drain electrode, the fourth gate electrode, the second source electrode, the fifth gate electrode, the third drain electrode, the sixth gate electrode, the third source electrode, the seventh gate electrode, the fourth drain electrode, and the eighth gate electrode. According to the present invention, a differential voltage controlled oscillator for RF oscillation operation in the broadband area is realized by minimizing generation of parasitic components.

    摘要翻译: 本发明涉及一种开关,负电阻单元和使用该开关的差分电压控制振荡器。 本发明包括沿第一方向设置的第一信号线,与第一信号线并联设置的第二信号线,以及第一至第四栅电极,第一至第三源电极和形成在第一信号线之间的第一至第四漏极 信号线和第二信号线,并且提供具有按照第一栅电极,第一漏电极,第二栅电极,第一源电极,第三栅电极,第二漏电极,第四电极的顺序的电极的开关 第二栅极电极,第二源极电极,第五栅极电极,第三漏极电极,第六栅极电极,第三源极电极,第七栅极电极,第四漏极电极和第八栅极电极。 根据本发明,通过最小化寄生分量的产生来实现在宽带区域中用于RF振荡操作的差分压控振荡器。

    Method of recycling spent flue gas denitration catalyst and method of determining washing time of spent flue gas denitration catalyst
    10.
    发明申请
    Method of recycling spent flue gas denitration catalyst and method of determining washing time of spent flue gas denitration catalyst 有权
    废烟气脱硝催化剂回收方法及废烟气脱硝催化剂洗涤时间的测定方法

    公开(公告)号:US20090005235A1

    公开(公告)日:2009-01-01

    申请号:US12007746

    申请日:2008-01-15

    IPC分类号: B01J38/48 B01J38/64 G01N33/00

    摘要: The present invention provides a method of recycling a spent flue gas denitration catalyst and a method of determining a washing time of the spent flue gas denitration catalyst. The method of recycling the spent flue gas denitration catalyst includes physically removing solids deposited in the spent flue gas denitration catalyst, removing poisoning substances deposited in the spent flue gas denitration catalyst by washing the spent flue gas denitration catalyst with a washing liquid for a washing time determined by measuring the hydrogen ion concentration of the washing liquid and drying the resulting spent flue gas denitration catalyst.

    摘要翻译: 本发明提供了废废气脱硝催化剂的再循环方法和废烟气脱硝催化剂的洗涤时间的测定方法。 废弃废气脱硝催化剂的再循环方法包括物理去除废烟道气脱硝催化剂中沉积的固体,通过用洗涤液洗涤废烟道脱硝催化剂洗涤废废气脱硝催化剂中的中毒物质,洗涤时间 通过测量洗涤液的氢离子浓度和干燥所得到的废烟气脱硝催化剂来测定。