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    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20120162836A1

    公开(公告)日：2012-06-28

    申请号：US13332861

    申请日：2011-12-21

    申请人： Futoshi FURUTA ,  Kenichi Osada

    发明人： Futoshi FURUTA ,  Kenichi Osada

    IPC分类号： H02H9/04 ,  H03K17/693

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/62 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H02H9/046

    摘要： In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.

    摘要翻译： 在堆叠式芯片系统中，连接到用于IO的TSV焊盘和开关电路的IO电路构成每个芯片中的IO通道，与最大预定堆栈数量一样多的IO通道耦合在一起并连接以构成IO组 ，并且芯片具有一个或多个这样的IO组。 用于IO的每个TSV焊盘与通孔连接到另一层的芯片中相同位置处的IO端子。 在插入器上，如果堆栈的实际数量小于堆栈的最大预定数量，则插入器上相邻IO组中IO的连接焊盘将通过导线连接。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08908345B2

    公开(公告)日：2014-12-09

    申请号：US13332861

    申请日：2011-12-21

    申请人： Futoshi Furuta ,  Kenichi Osada

    发明人： Futoshi Furuta ,  Kenichi Osada

    IPC分类号： H01L27/02 ,  H02H9/04 ,  H01L25/065 ,  H01L23/62 ,  H01L23/48

    CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L23/62 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/15311 ,  H02H9/046

    摘要： In a stacked chip system, an IO circuit connected to a TSV pad for IO and a switch circuit constitute an IO channel in each chip, the IO channels as many as the maximum scheduled number of stacks are coupled together and connected to constitute an IO group, and the chip has one or more such IO groups. Each TSV pad for IO is connected with a through via to an IO terminal at the same position in a chip of another layer. On an interposer, if the actual number of stacks is less than the maximum scheduled number of stacks, connection pads for IO in adjacent IO groups on the interposer are connected via a conductor.

    摘要翻译： 在堆叠式芯片系统中，连接到用于IO的TSV焊盘和开关电路的IO电路构成每个芯片中的IO通道，与最大预定堆栈数量一样多的IO通道耦合在一起并连接以构成IO组 ，并且芯片具有一个或多个这样的IO组。 用于IO的每个TSV焊盘与通孔连接到另一层的芯片中相同位置处的IO端子。 在插入器上，如果堆栈的实际数量小于堆栈的最大预定数量，则插入器上相邻IO组中IO的连接焊盘将通过导线连接。

    Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array
    7.
    发明授权
    Semiconductor integrated circuit device including SRAM cell array and a wiring layer for supplying voltage to well regions of SRAM cells provided on a region exterior of SRAM cell array 有权
    包括SRAM单元阵列的半导体集成电路器件和用于向SRAM单元阵列的外部区域上提供的SRAM单元的阱区域提供电压的布线层

    公开(公告)号：US09286968B2

    公开(公告)日：2016-03-15

    申请号：US13616435

    申请日：2012-09-14

    申请人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    发明人： Kenichi Osada ,  Masataka Minami ,  Shuji Ikeda ,  Koichiro Ishibashi

    IPC分类号： H01L29/76 ,  H01L27/11 ,  G11C11/412

    CPC分类号： H01L27/1104 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11 ,  H01L29/4916 ,  H01L29/783 ,  Y10S257/904

    摘要： Prior known static random access memory (SRAM) cells required that a diffusion layer be bent into a key-like shape in order to make electrical contact with a substrate with a P-type well region formed therein, which would result in a decrease in asymmetry leading to difficulty in micro-patterning. To avoid this problem, the P-type well region in which an inverter making up an SRAM cell is formed is subdivided into two portions, which are disposed on the opposite sides of an N-type well region NW1 and are formed so that a diffusion layer forming a transistor has no curvature while causing the layout direction to run in a direction parallel to well boundary lines and bit lines. At intermediate locations of an array, regions for use in supply power to the substrate are formed in parallel to word lines.

    摘要翻译： 现有已知的静态随机存取存储器（SRAM）单元需要将扩散层弯曲成键状形状，以便与其中形成有P型阱区的衬底电接触，这将导致不对称性的降低 导致微图案化困难。 为了避免这个问题，构成SRAM单元的逆变器的P型阱区被细分成两部分，它们设置在N型阱区NW1的相对侧上，并形成为扩散 形成晶体管的层没有曲率，同时使得布局方向在平行于阱边界线和位线的方向上运行。 在阵列的中间位置处，与基板平行地形成用于向基板供电的区域。

    Detection system, semiconductor device, and data processing device
    8.
    发明授权
    Detection system, semiconductor device, and data processing device 失效
    检测系统，半导体器件和数据处理器件

    公开(公告)号：US08633684B2

    公开(公告)日：2014-01-21

    申请号：US12917523

    申请日：2010-11-02

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    IPC分类号： G01R5/14

    CPC分类号： G06F1/3203 ,  G06F1/206 ,  H01L21/67276 ,  Y02D10/16

    摘要： To provide an LSI having a low power mode that can prevent an apparatus on which the LSI is mounted from resulting in performance degradation, etc. even when its electric power is not reduced in the low power mode. Devised is a circuit that instructs an operation mode and detects whether the LSI operates as specified by the mode, and that measures a current at the time of the low power mode in a pseudo manner and, if despite having shifted to the low power mode, the current is not reduced actually, issues an alarm signal.

    摘要翻译： 为了提供具有低功率模式的LSI，即使在低功率模式下其电力没有降低的情况下，也可以防止LSI的装置在其中导致性能劣化等。 设计的是指示操作模式并且检测LSI是否以模式指定的方式操作的电路，并且以伪方式测量低功率模式时的电流，并且如果尽管已经转移到低功率模式， 电流实际上没有减少，发出报警信号。

    Semiconductor integrated circuit and manufacturing method thereof
    9.
    发明授权
    Semiconductor integrated circuit and manufacturing method thereof 失效
    半导体集成电路及其制造方法

    公开(公告)号：US08531872B2

    公开(公告)日：2013-09-10

    申请号：US13350340

    申请日：2012-01-13

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Shigenobu Komatsu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/417

    摘要： High manufacturing yield is realized and variation in threshold voltage of each MOS transistor in a CMOS·SRAM is compensated. Body bias voltages are applied to wells for MOS transistors of each SRAM memory cell in any active mode of an information holding operation, a write operation and a read operation of an SRAM. Threshold voltages of PMOS and NMOS transistors of the SRAM are first measured. Control information is programmed into control memories according to results of determination. Levels of the body bias voltages are adjusted based on the programs so that variations in the threshold voltages of the MOS transistors of the CMOS·SRAM are controlled to a predetermined error span. Body bias voltage corresponding to a reverse body bias or an extremely shallow forward body bias is applied to a substrate for the MOS transistors with an operating voltage applied to the source of each MOS transistor.

    摘要翻译： 实现了高制造成品率，补偿了CMOS·SRAM中的每个MOS晶体管的阈值电压的变化。 在SRAM的信息保持操作，写入操作和读取操作的任何活动模式中，将体偏置电压施加到每个SRAM存储器单元的MOS晶体管的阱。 首先测量SRAM的PMOS和NMOS晶体管的阈值电压。 控制信息根据确定结果被编程到控制存储器中。 基于程序调整体偏置电压的电平，使得CMOS·SRAM的MOS晶体管的阈值电压的变化被控制到预定的误差范围。 将对应于反体偏置或非常浅的正向体偏置的体偏置电压施加到施加到每个MOS晶体管的源极的工作电压的MOS晶体管的衬底。

    Information technology equipment
    10.
    发明授权
    Information technology equipment 有权
    信息技术设备

    公开(公告)号：US08451050B2

    公开(公告)日：2013-05-28

    申请号：US12987112

    申请日：2011-01-08

    申请人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    发明人： Masanao Yamaoka ,  Kenichi Osada ,  Minoru Motoyoshi ,  Tetsuya Fukuoka

    IPC分类号： G05F1/10

    CPC分类号： G06F1/3203 ,  H03K19/0016

    摘要： Information technology equipment includes a circuit block, a local power source line for supplying a power source to the circuit block, a power source line, and a first transistor which is provided with a source-drain path thereof between the power source line and the local power source line, in which the first transistor is controlled to an OFF state in a first state, and is controlled to an ON state in a second state, and when the first state is shifted to the second state, the first transistor is controlled such that a rate of changing a current flowing in the source-drain path of the first transistor does not exceed a predetermined value.

    摘要翻译： 信息技术设备包括电路块，用于向电路块提供电源的局部电源线，电源线和在电源线和本地电源线之间设置有源极 - 漏极路径的第一晶体管 电源线，其中第一晶体管在第一状态下被控制为OFF状态，并且在第二状态下被控制为ON状态，并且当第一状态转移到第二状态时，第一晶体管被控制为 改变在第一晶体管的源极 - 漏极路径中流动的电流的速率不超过预定值。