公开(公告)号：US09093474B2

公开(公告)日：2015-07-28

申请号：US13600616

申请日：2012-08-31

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC分类号： H01L29/66712 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66719 ,  H01L29/7802 ,  H01L29/7811

摘要： A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

摘要翻译： 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。

公开(公告)号：US20130248988A1

公开(公告)日：2013-09-26

申请号：US13607697

申请日：2012-09-08

申请人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/02

CPC分类号： H01L29/7827 ,  H01L21/02697 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device includes a semiconductor substrate and a plurality of gate electrodes including a part extended in a first direction in a plane parallel with the semiconductor substrate. The semiconductor substrate has a second semiconductor layer including a plurality of first conductive type pillars and second conductive type second pillars that are disposed on the first semiconductor layer, extending in the first direction in the plane parallel with the semiconductor substrate and in a third direction intersecting with a second direction orthogonal to the first direction, and arranged adjacent to each other in an alternate manner.

摘要翻译： 半导体器件包括半导体衬底和多个栅电极，其包括在与半导体衬底平行的平面中沿第一方向延伸的部分。 所述半导体衬底具有包括多个第一导电型柱和第二导电型第二柱的第二半导体层，所述第二导电型柱和第二导电型第二柱设置在所述第一半导体层上，在与所述半导体衬底平行的平面中沿所述第一方向延伸，并且在第三方向上相交 具有与第一方向正交的第二方向，并且以交替的方式彼此相邻布置。

公开(公告)号：US20130248979A1

公开(公告)日：2013-09-26

申请号：US13610532

申请日：2012-09-11

申请人： Syotaro Ono ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Hiroaki Yamashita

发明人： Syotaro Ono ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Hiroaki Yamashita

IPC分类号： H01L27/088

CPC分类号： H01L29/407 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： A power semiconductor device according to an embodiment includes an element portion in which MOSFET elements are provided and a termination portion provided around the element portion, and has pillar layers provided respectively in parallel to each other in a semiconductor substrate. The device includes a first trench and a first insulation film. The first trench is provided between end portions of the pillar layers, in the semiconductor substrate at the termination portion exposed from a source electrode of the MOSFET elements. The first insulation film is provided on a side surface and a bottom surface of the first trench.

摘要翻译： 根据实施例的功率半导体器件包括其中设置MOSFET元件的元件部分和设置在元件部分周围的端接部分，并且在半导体衬底中分别彼此平行地设置有柱层。 该器件包括第一沟槽和第一绝缘膜。 第一沟槽设置在从MOSFET元件的源电极露出的终端部分的半导体衬底中的柱层的端部之间。 第一绝缘膜设置在第一沟槽的侧表面和底表面上。

公开(公告)号：US08482028B2

公开(公告)日：2013-07-09

申请号：US13424340

申请日：2012-03-19

申请人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Toshiyuki Naka ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/772 ,  H01L21/335

CPC分类号： H01L29/7811 ,  H01L21/266 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/66712

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，以及周期性阵列结构，其具有第一导电类型的第二半导体层和周期性排列在第一半导体上的第二导电类型的第三半导体层 层在与第一半导体层的主表面平行的方向上。 第二半导体层和第三半导体层以点形式设置在第一半导体层上。 周期性阵列结构的最外围部分中的周期性结构不同于最外周部​​分以外的部分的周期性阵列结构的周期性结构。

公开(公告)号：US20120074461A1

公开(公告)日：2012-03-29

申请号：US13235302

申请日：2011-09-16

申请人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/331 ,  H01L29/739

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238

摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

摘要翻译： 根据实施例，半导体器件包括设置在第一半导体层上并包括第一柱和第二柱的第二半导体层。 第一控制电极设置在第二半导体层的沟槽中，第二控制电极设置在第二半导体层上并连接到第一控制电极。 除了第二控制电极下方的部分之外，在第二半导体层的表面上设置第一半导体区域。 第二半导体区域设置在第一半导体区域的表面上，第二半导体区域与第二控制电极下方的部分分开，第三半导体区域设置在第一半导体区域上。 第一主电极与第一半导体层电连接，第二主电极与第二和第三半导体区域电连接。

公开(公告)号：US20120056262A1

公开(公告)日：2012-03-08

申请号：US13052028

申请日：2011-03-18

申请人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru SAITO ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78

CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, an embedded electrode, a control electrode, a fourth semiconductor layer of the second conductivity type, a first main electrode, and a second main electrode. The second semiconductor layer is provided on the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The embedded electrode is provided in a first trench via a first insulating film. The first trench penetrates through the second semiconductor layer from a surface of the third semiconductor layer to reach the first semiconductor layer. The control electrode is provided above the embedded electrode via a second insulating film in the first trench. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench. The second trench penetrates through the second semiconductor layer from the surface of the third semiconductor layer to reach the first semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer. The second main electrode is provided in the second trench and connected to the second semiconductor layer, the third semiconductor layer and the fourth semiconductor layer. The embedded electrode is electrically connected to one of the second main electrode and the control electrode. A Schottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体层，第二导电类型的第二半导体层，第一导电类型的第三半导体层，嵌入电极，控制电极，第四半导体 第二导电类型的层，第一主电极和第二主电极。 第二半导体层设置在第一半导体层上。 第三半导体层设置在第二半导体层上。 嵌入式电极经由第一绝缘膜设置在第一沟槽中。 第一沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。 控制电极通过第一沟槽中的第二绝缘膜设置在嵌入电极的上方。 第四半导体层选择性地设置在第一半导体层中并连接到第二沟槽的下端。 第二沟槽从第三半导体层的表面穿过第二半导体层到达第一半导体层。 第一主电极电连接到第一半导体层。 第二主电极设置在第二沟槽中并连接到第二半导体层，第三半导体层和第四半导体层。 嵌入电极与第二主电极和控制电极中的一个电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

公开(公告)号：US07190674B2

公开(公告)日：2007-03-13

申请号：US10281366

申请日：2002-10-25

申请人： Takahiro Kobayakawa ,  Hiroaki Yamashita

发明人： Takahiro Kobayakawa ,  Hiroaki Yamashita

IPC分类号： H04L12/66 ,  H04L12/28 ,  H04L12/26

CPC分类号： H04L49/508 ,  H04L47/22 ,  H04L47/24 ,  H04L47/50 ,  H04L47/56 ,  H04L49/30 ,  H04L49/506

摘要： In a packet scheduler, an arithmetic-operation controlling means designates output ports in a time-sharing manner and a parallel arithmetic operation means performs an arithmetic operation common with the queues of each designated output port to obtain packet output completion due times (evaluation factors) of the top packets of queues of each output port. Intra-port selecting means selects the evaluation factor of a packet that is to be preferentially output for each output port based on the result of the arithmetic operations. Then inter-port selecting means determines one to be most-preferentially output from the top packets selected based on the selected evaluation factors and the bandwidths for the output ports. Therefore, an apparatus for controlling packet output having such a packet scheduler can realize accurately control bandwidths of a plurality of queues, high-speed processing and the reduced size thereby being incorporated in hardware.

摘要翻译： 在分组调度器中，算术运算控制装置以分时方式指定输出端口，并行算术运算装置执行与各指定输出端口的队列相同的算术运算，以获得分组输出完成到期（评估因子） 的每个输出端口的最高队列数据包。 内部端口选择装置根据算术运算的结果，选择要对每个输出端口优先输出的分组的评估因子。 然后，端口间选择装置根据所选择的评估因子和输出端口的带宽确定从最高分组选出的最优先输出。 因此，具有这种分组调度器的用于控制分组输出的装置可以精确地实现多个队列的控制带宽，高速处理和减小的尺寸，从而被并入硬件。

公开(公告)号：US6097739A

公开(公告)日：2000-08-01

申请号：US841872

申请日：1997-05-05

申请人： Hiroaki Yamashita

发明人： Hiroaki Yamashita

IPC分类号： H04N19/423 ,  H04J3/07 ,  H04L12/28 ,  H04L12/70 ,  H04N7/24 ,  H04N19/00 ,  H04N19/70 ,  H04Q3/00

CPC分类号： H04N21/23611

摘要： A data transfer rate control method inserts a stuff packet in real time to resolve the problem present in an ATM transmission for MPEG data. The method, for controlling a data transfer rate at which coded data are transferred in an asynchronous transfer mode may include the steps of: forming the coded data for an AAL layer (ATM Adaptation Layer); calculating an insertion timing for insertion of a NULL packet; inserting the NULL packet into the coded data of the AAL layer in consonance with the insertion timing, obtained by the calculation, for the NULL packet; and transferring, in the asynchronous transfer mode, the coded data of the AAL layer into which the NULL packet is inserted.

摘要翻译： 数据传输速率控制方法实时插入填充数据包以解决MPEG数据的ATM传输中存在的问题。 用于控制以异步传送模式传送编码数据的数据传送速率的方法可以包括以下步骤：形成用于AAL层（ATM适配层）的编码数据; 计算用于插入NULL分组的插入时间; 将NULL分组插入到AAL层的编码数据中，这符合通过计算获得的用于NULL分组的插入定时; 并且在异步传送模式中传送其中插入NULL分组的AAL层的编码数据。

公开(公告)号：US5918000A

公开(公告)日：1999-06-29

申请号：US539774

申请日：1995-10-05

申请人： Hiroaki Yamashita ,  Yasushi Inamoto ,  Kiichi Matsuda

发明人： Hiroaki Yamashita ,  Yasushi Inamoto ,  Kiichi Matsuda

IPC分类号： G06F13/16 ,  G06F3/06 ,  G06F11/20 ,  G06F13/36 ,  G11B20/12 ,  G11B20/18 ,  G06F11/08

CPC分类号： G06F11/2094 ,  G06F3/0625 ,  G06F3/0658 ,  G06F3/0689 ,  G11B20/1252 ,  G11B20/1833 ,  G11B20/1883 ,  G11B2220/20 ,  Y02B60/1246

摘要： A data transfer control device and controlling method in which data on a storage medium is read continuously. The data transfer control device includes M storage units each for storing respectively at least two kinds of different data among N kinds of data in memory regions, a transmission control element for transmitting the N kinds of data and a spare storage unit for storing at least one kind of data among said N kinds of data. The transfer control device includes a judging element for judging whether accessing any one of the M storage units must be halted. Switching element for switching a memory region to the spare storage unit and the remaining (M-1) storage unit when the judging element judges that accessing must be halted and then the switching element performs an accessing operation. The data transfer control device can suppress an increase in the device forming cost, power consumption, and installation area, and can increase the amount of data which can be stored according to the number of storage units installed.

摘要翻译： 一种数据传送控制装置及其中持续读取存储介质上的数据的控制方法。 数据传送控制装置包括M个存储单元，每个存储单元分别存储存储区域中的N种数据中的至少两种不同数据，用于发送N种数据的传输控制元件和用于存储至少一个 所述N种数据中的数据种类。 传送控制装置包括用于判断是否必须停止访问M个存储单元中的任何一个的判断元件。 当判断元件判定该访问必须停止，然后开关元件执行访问操作时，用于将存储器区域切换到备用存储单元和剩余（M-1）个存储单元。 数据传输控制装置可以抑制装置成本成本，功耗和安装面积的增加，并且可以根据安装的存储单元的数量增加可以存储的数据量。

公开(公告)号：US5173361A

公开(公告)日：1992-12-22

申请号：US642501

申请日：1991-01-17

申请人： Hiroaki Yamashita ,  Takashi Toyota

发明人： Hiroaki Yamashita ,  Takashi Toyota

IPC分类号： F16G1/28 ,  B29D29/00 ,  B32B15/02 ,  B32B25/02 ,  C08J5/04 ,  F16G1/12 ,  F16G5/06 ,  F16G5/10

CPC分类号： F16G5/10 ,  F16G1/12 ,  Y10S428/903 ,  Y10S428/909 ,  Y10T152/10765 ,  Y10T428/249942

摘要： A fiber reinforced composite belt in which a stainless steel fiber aggregate having a diameter of from 5 to 50 .mu.m and impregnated with 1 to 10% by weight of a thermosetting resin such as an epoxy resin is buried as a reinforcing material in a base material for belt, and a process for preparing the above-mentioned fiber reinforced composite belt are provided. This fiber reinforced composite belt is much more excellent in flex resistance, durability, water resistance and coefficient of linear expansion, as compared with not only a rubber belt and a synthetic resin elastomer belt but also belts reinforced by directly burying a stainless steel fiber and a steel fiber in the rubber.