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    Partial response decision-feedback equalization with adaptation based on edge samples
    1.
    发明授权
    Partial response decision-feedback equalization with adaptation based on edge samples 有权
    基于边缘样本的部分响应决策反馈均衡与适应

    公开(公告)号：US08477834B2

    公开(公告)日：2013-07-02

    申请号：US12513898

    申请日：2007-11-09

    申请人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    发明人： Brian S. Leibowitz ,  Hae-Chang Lee ,  Jihong Ren ,  Ruwan Ratnayake

    IPC分类号： H03H7/30 ,  H04L27/06 ,  H04B1/10

    CPC分类号： H04L25/03057 ,  G06F13/38 ,  H04L25/03019 ,  H04L25/0307 ,  H04L2025/03369 ,  H04L2025/03617

    摘要： A device (102) implements data reception with edge-based partial response decision feedback equalization. In an example embodiment, the device implements a tap weight adapter circuit (114) that sets the tap weights that are used for adjustment of a received data signal (104). The tap weight adapter circuit (119) sets the tap weights based on previously determined data values and input from an edge analysis of the received data signal using a set of edge samplers. The edge analysis (116) may include adjusting the sampled data signal by the tap weights determined by the tap weight adapter circuit. A clock generation circuit (220) generates an edge clock signal to control the edge sampling performed by the set of edge samplers. The edge clock signal may be generated as a function of the signals of the edge samplers and prior data values determined by the equalizer.

    摘要翻译： 设备（102）利用基于边缘的部分响应判决反馈均衡来实现数据接收。 在一个示例性实施例中，该装置实现一个抽头权重适配器电路（114），其设置用于调整接收到的数据信号（104）的抽头权重。 抽头重量适配器电路（119）基于先前确定的数据值设置抽头权重，并使用一组边缘采样器从接收数据信号的边缘分析输入。 边缘分析（116）可以包括通过由抽头权重适配器电路确定的抽头权重来调整采样数据信号。 时钟发生电路（220）生成边沿时钟信号以控制由边缘采样器组执行的边缘采样。 可以根据边缘采样器的信号和由均衡器确定的先前数据值来生成边沿时钟信号。

    "> Integrated Circuit Having Receiver Jitter Tolerance (
    2.
    发明申请
    Integrated Circuit Having Receiver Jitter Tolerance ("JTOL") Measurement 有权
    具有接收机抖动容限（“JTOL”）测量的集成电路

    公开(公告)号：US20130093433A1

    公开(公告)日：2013-04-18

    申请号：US13621783

    申请日：2012-09-17

    申请人： Hae-Chang Lee ,  Jaeha Kim ,  Brian Leibowitz

    发明人： Hae-Chang Lee ,  Jaeha Kim ,  Brian Leibowitz

    IPC分类号： G01R29/26

    CPC分类号： G01R29/26 ,  G01R31/31709 ,  G01R31/31725

    摘要： An integrated circuit capable of on-chip jitter tolerance measurement includes a jitter generator circuit to produce a controlled amount of jitter that is injected into at least one clock signal, and a receive circuit to sample an input signal according to the at least one clock signal. The sampled data values output from the receiver are used to evaluate the integrated circuit's jitter tolerance.

    摘要翻译： 能够进行片上抖动容限测量的集成电路包括：抖动发生器电路，用于产生被注入到至少一个时钟信号中的受控量的抖动;以及接收电路，用于根据至少一个时钟信号对输入信号进行采样 。 从接收器输出的采样数据值用于评估集成电路的抖动容限。

    Techniques for Phase Detection
    3.
    发明申请
    Techniques for Phase Detection 审中-公开
    相位检测技术

    公开(公告)号：US20120218001A1

    公开(公告)日：2012-08-30

    申请号：US13505714

    申请日：2010-10-31

    申请人： Brian Leibowitz ,  Hae-Chang Lee ,  Farshid Aryanfar ,  Kun-Yung Chang ,  Jie Shen

    发明人： Brian Leibowitz ,  Hae-Chang Lee ,  Farshid Aryanfar ,  Kun-Yung Chang ,  Jie Shen

    IPC分类号： H03D13/00

    CPC分类号： H03D13/00 ,  H03L7/08 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/085

    摘要： A phase detection circuit can include two phase detectors that each generate a non-zero output in response to input signals being aligned in phase. The input signals are based on two periodic signals. The phase detection circuit subtracts the output signal of one phase detector from the output signal of the other phase detector to generate a signal having a zero value when the periodic signals are in phase. Alternatively, a phase detector generates a phase comparison signal indicative of a phase difference between periodic signals. The phase comparison signal has a non-zero value in response to input signals to the phase detector being aligned in phase. The input signals are based on the periodic signals. An output circuit receives the phase comparison signal and generates an output having a zero value in response to the periodic signals being aligned in phase.

    摘要翻译： 相位检测电路可以包括两个相位检测器，每个相位检测器响应于同相对准的输入信号而产生非零输出。 输入信号基于两个周期信号。 相位检测电路从另一相位检测器的输出信号中减去一相位检测器的输出信号，当周期信号同相时产生具有零值的信号。 或者，相位检测器产生指示周期信号之间的相位差的相位比较信号。 相位比较信号响应于相位检测器的相位输入信号具有非零值。 输入信号基于周期信号。 输出电路接收相位比较信号，并响应于同相对齐的周期信号产生具有零值的输出。

    Signal Distribution Networks and Related Methods
    4.
    发明申请
    Signal Distribution Networks and Related Methods 有权
    信号分配网络及相关方法

    公开(公告)号：US20120187988A1

    公开(公告)日：2012-07-26

    申请号：US13498884

    申请日：2010-10-09

    申请人： Farshid Aryanfar ,  Hae-Chang Lee ,  Kun-Yung Chang ,  Ting Wu ,  Carl Werner ,  Masoud Koochakzadeh

    发明人： Farshid Aryanfar ,  Hae-Chang Lee ,  Kun-Yung Chang ,  Ting Wu ,  Carl Werner ,  Masoud Koochakzadeh

    IPC分类号： H03L7/06

    CPC分类号： H03L7/093 ,  G06F1/10 ,  H03L7/0802

    摘要： A signal distribution network has segments that each have a buffer circuit, a transmission line coupled to the buffer circuit, an inductor coupled to the buffer circuit through the transmission line, and a variable capacitance circuit coupled to the inductor and coupled to the buffer circuit through the transmission line. A capacitance of the variable capacitance circuit is set to determine a phase and an amplitude of a signal transmitted through the transmission line. A signal distribution network can include a phase detector, a loop filter circuit, and a resonant delay circuit. The phase detector compares a phase of a first periodic signal to a phase of a second periodic signal. The resonant delay circuit has a variable impedance circuit having an impedance that varies based on changes in an output signal of the loop filter circuit.

    摘要翻译： 信号分配网络具有每个段具有缓冲电路，耦合到缓冲电路的传输线，通过传输线耦合到缓冲电路的电感器，以及耦合到电感器的可变电容电路，并通过 传输线。 可变电容电路的电容被设定为确定通过传输线传输的信号的相位和幅度。 信号分配网络可以包括相位检测器，环路滤波器电路和谐振延迟电路。 相位检测器将第一周期信号的相位与第二周期信号的相位进行比较。 谐振延迟电路具有可变阻抗电路，其具有基于环路滤波器电路的输出信号的变化而变化的阻抗。

    Driver Supporting Multiple Signaling Modes
    5.
    发明申请
    Driver Supporting Multiple Signaling Modes 有权
    驱动程序支持多种信令模式

    公开(公告)号：US20110316590A1

    公开(公告)日：2011-12-29

    申请号：US13255844

    申请日：2010-05-07

    申请人： Ken Kun-Yung Chang ,  Kashinath Prabhu ,  Hae-Chang Lee

    发明人： Ken Kun-Yung Chang ,  Kashinath Prabhu ,  Hae-Chang Lee

    IPC分类号： H03K3/00

    CPC分类号： H03K19/018585 ,  H03K19/018528

    摘要： A driver supports differential and single-ended signaling modes. Complementary transistors with a common tail node are provided with complementary input signals in the differential mode. A current source coupled to the tail node maintains a relatively high tail impedance and a constant tail current in the differential mode. The tail node is set to a low impedance in single-ended modes to decouple the two transistors, allowing them to amplify uncorrelated input signals. The current source thaws multiple current levels in the single-ended mode to compensate for changes in tail current that result from changes in the relative values of the uncorrelated data in the single-ended modes. A termination block provides termination resistance in the differential mode, pull-up transistors in a single-ended mode that employs push-pull drivers, and is omitted in a single-ended mode that lacks driver-side termination.

    摘要翻译： 驱动程序支持差分和单端信令模式。 具有公共尾节点的互补晶体管在差分模式下被提供有互补输入信号。 耦合到尾节点的电流源在差分模式下保持相对较高的尾部阻抗和恒定的尾部电流。 尾端节点在单端模式下设置为低阻抗，以对两个晶体管进行去耦，从而使它们能够放大不相关的输入信号。 当前的源解决了单端模式下的多个电流电平，以补偿由单端模式中不相关数据的相对值变化引起的尾电流变化。 端接模块提供差分模式下的终端电阻，采用推挽驱动器的单端模式的上拉晶体管，并且在缺少驱动器侧端接的单端模式下被省略。

    APPARATUS AND METHODS FOR DIFFERENTIAL SIGNAL RECEIVING
    6.
    发明申请
    APPARATUS AND METHODS FOR DIFFERENTIAL SIGNAL RECEIVING 有权
    差异信号接收的装置和方法

    公开(公告)号：US20100272216A1

    公开(公告)日：2010-10-28

    申请号：US12746018

    申请日：2008-10-29

    申请人： Brian S. Liebowitz ,  Jaeha Kim ,  Hae-Chang Lee

    发明人： Brian S. Liebowitz ,  Jaeha Kim ,  Hae-Chang Lee

    IPC分类号： H04L27/00 ,  G01R29/00

    CPC分类号： H04L7/0338 ,  H03K5/133 ,  H04L7/0008

    摘要： A differential signal receiver 106 implements intra-pair skew compensation for improving data transfer on a differential channel. In an embodiment, the receiver implements sampling by—multiple clocks with different phases such that the signals of the differential channel may be separately or individually time adjusted to account for skew between them so that they may be differentially compared for data resolution. In one embodiment, a positive sampler and negative sampler are controlled by distinct clock signals to permit, at different times, sampling and holding of the positive and negative signals representing a data bit on the differential channel. A differential decision circuit may then differentially resolve the data using a latter one of the distinct clock signals. Timing generation circuitry for producing the offset clocks may include a skew detector that permits dynamic adjustment of the different clock signals according to skew associated with the signals of the differential channel.

    摘要翻译： 差分信号接收机106实现对对偏斜补偿，以改善差分信道上的数据传输。 在一个实施例中，接收机以不同的相位实现采样多个时钟，使得差分信道的信号可以单独地或单独地进行时间调整以解决它们之间的偏斜，使得它们可以被差分地比较用于数据分辨率。 在一个实施例中，正采样器和负采样器由不同的时钟信号控制，以允许在不同时间对表示差分信道上的数据位的正和负信号进行采样和保持。 然后差分判决电路可以使用不同时钟信号中的后一个来差分地解析数据。 用于产生偏移时钟的定时发生电路可以包括偏斜检测器，其允许根据与差分信道的信号相关联的偏斜动态调整不同的时钟信号。