公开(公告)号：US06295579B1

公开(公告)日：2001-09-25

申请号：US09070851

申请日：1998-05-01

申请人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

发明人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

IPC分类号： G06F1200

CPC分类号： G06F12/0813 ,  G06F12/0848 ,  G06F2212/272

摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

摘要翻译： 并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。 并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。 每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

公开(公告)号：US5778429A

公开(公告)日：1998-07-07

申请号：US497751

申请日：1995-07-03

申请人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

发明人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0848 ,  G06F2212/272

摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

摘要翻译： 并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。 并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。 每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

公开(公告)号：US5898883A

公开(公告)日：1999-04-27

申请号：US368618

申请日：1995-01-04

申请人： Hiroaki Fujii ,  Toshiaki Tarui ,  Naonobu Sukegawa

发明人： Hiroaki Fujii ,  Toshiaki Tarui ,  Naonobu Sukegawa

IPC分类号： G06F15/17 ,  G06F12/02 ,  G06F15/16

CPC分类号： G06F12/0284

摘要： To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.

摘要翻译： 为了增加整个并行处理计算机系统的可用存储器的容量并有效地利用地址空间而不浪费，可变长度的全局/局部分配字段被提供在固定长度的地址中。 当本地设置该字段时，该地址被用作本地处理器引用的本地存储器区域的地址。 当分配被全局设置时，剩余地址是可变长度的逻辑处理器号码（该数字被转换成物理处理器号码）和可变长度偏移地址，用于指定属于全局区域中的处理器的全局存储器区域 一组处理器的存储器，该组的所有处理器可以引用全局存储器。 存储器访问接口执行对本地处理器的存储器的本地或全局区域或另一处理器的存储器的全局区域的存储器访问。

公开(公告)号：US5606686A

公开(公告)日：1997-02-25

申请号：US328759

申请日：1994-10-24

申请人： Toshiaki Tarui ,  Naonobu Sukegawa ,  Hiroaki Fujii ,  Katsuyoshi Kitai

发明人： Toshiaki Tarui ,  Naonobu Sukegawa ,  Hiroaki Fujii ,  Katsuyoshi Kitai

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F15/173

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F15/17393 ,  G06F2212/2542

摘要： A main memory shared by plural processing units in a parallel computer system is composed of plural partial main memories. A directory for each data line of the main memory is generated after the data line has been cached in one of the processing units. The directory is held in one of the partial main memories in place of the data line. The directory indicates a processing unit which has cached the data line. A status bit C provided for the data line is set. If a subsequent read request is given to the data line, the status C bit is checked and the directory is used to identify a processing unit that has cached the data line. The request is transferred to the identified processing unit, and the data line is transferred from that processing unit to the processing unit that has issued the request. If a processing unit that has cached the data line has replaced the data line, it is checked if there is a processing unit that has cached the data line. If there is none, the data line is written back into the one partial main memory. If there is, the data line is not written back. Another status bit RO is also used for each data line. It indicates if the data line is read only. If a data line is read only, generation of the directory and storing it in the partial main memory is prohibited.

摘要翻译： 并行计算机系统中的多个处理单元共享的主存储器由多个部分主存储器构成。 在数据线已被缓存在一个处理单元中之后，生成主存储器的每条数据线的目录。 该目录被保存在一部分主存储器中以代替数据线。 该目录指示已经缓存数据线的处理单元。 设置为数据线提供的状态位C。 如果向数据线提供后续的读取请求，则检查状态C位，并使用该目录来标识缓存数据线的处理单元。 该请求被传送到所识别的处理单元，并且数据线从该处理单元传送到已经发出请求的处理单元。 如果缓存数据线的处理单元已经取代了数据线，则检查是否存在缓存数据行的处理单元。 如果没有，则数据线被写回到一个部分主存储器中。 如果有，数据行不会被写回。 每个数据线也使用另一个状态位RO。 它指示数据行是否为只读。 如果数据线是只读的，则禁止生成目录并将其存储在部分主存储器中。

公开(公告)号：US20080222434A1

公开(公告)日：2008-09-11

申请号：US12068086

申请日：2008-02-01

申请人： Masaaki Shimizu ,  Naonobu Sukegawa

发明人： Masaaki Shimizu ,  Naonobu Sukegawa

IPC分类号： G06F9/46 ,  G06F1/26

CPC分类号： G06F1/3203 ,  G06F1/329 ,  G06F9/5027 ,  Y02D10/22 ,  Y02D10/24

摘要： Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job.

摘要翻译： 提供了一种在计算机系统中使用的方法，其包括至少一个主计算机，所述方法包括管理由主计算机执行的作业和主计算机的电源，所述方法包括以下过程：接收作业; 存储所接收的作业; 调度存储作业的执行计划; 基于作业的执行计划确定执行主计算机的功率控制的定时; 当达到确定的执行功率控制的定时时，确定主计算机执行功率控制; 控制所确定的主机的电源; 并执行预定作业。

公开(公告)号：US07159079B2

公开(公告)日：2007-01-02

申请号：US10886036

申请日：2004-07-08

申请人： Naonobu Sukegawa

发明人： Naonobu Sukegawa

IPC分类号： G06F13/00

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F12/0831

摘要： A splittable/connectible bus 140 and a network 1000 for transmitting coherence transactions between CPUs are provided between the CPUs, and a directory 160 and a group setup register 170 for storing bus-splitting information are provided in a directory control circuit 150 that controls cache invalidation. The bus is dynamically set to a split or connected state to fit a particular execution form of a job, and the directory control circuit uses the directory in order to manage all inter-CPU coherence control sequences in response to the above setting, while at the same time, in accordance with information of the group setup register, omitting dynamically bus-connected CPU-to-CPU cache coherence control, and conducting only bus-split CPU-to-CPU cache coherence control through the network.Thus, decreases in performance scalability due to an inter-CPU coherence-processing overhead are relieved in a system having multiple CPUs and guaranteeing inter-CPU cache coherence by use of hardware.

摘要翻译： 在CPU之间提供可拆卸/可连接总线140和用于在CPU之间传输相干事务的网络1000，并且在目录控制电路150中提供用于存储总线分解信息的目录160和组设置寄存器170，其控制高速缓存无效 。 总线被动态设置为分割或连接状态以适合作业的特定执行形式，并且目录控制电路使用该目录以便响应于上述设置来管理所有CPU间相干控制序列，而在 同时，根据组设置寄存器的信息，省略动态总线连接的CPU到CPU缓存一致性控制，并通过网络进行总线分割CPU到CPU缓存一致性控制。 因此，在具有多个CPU的系统中减轻了由于CPU间相干处理开销引起的性能可扩展性的降低，并且通过使用硬件来保证CPU间高速缓存的一致性。

公开(公告)号：US20080059715A1

公开(公告)日：2008-03-06

申请号：US11705410

申请日：2007-02-13

申请人： Aki Tomita ,  Naonobu Sukegawa

发明人： Aki Tomita ,  Naonobu Sukegawa

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A processor reads a program including a prefetch command and a load command and data from a main memory, and executes the program. The processor includes: a processor core that executes the program; a L2 cache that stores data on the main memory for each predetermined unit of data storage; and a prefetch unit that pre-reads the data into the L2 cache from the main memory on the basis of a request for prefetch from the processor core. The prefetch unit includes: a L2 cache management table including an area in which a storage state is held for each position in the unit of data storage of the L2 cache and an area in which a request for prefetch is reserved; and a prefetch control unit that instructs, the L2 cache to perform the request for prefetch reserved or the request for prefetch from the processor core.

摘要翻译： 处理器从主存储器读取包括预取命令和加载命令以及数据的程序，并执行该程序。 处理器包括：执行程序的处理器核心; L2缓存，用于在每个预定的数据存储单元上存储主存储器上的数据; 以及预取单元，其基于来自处理器核的预取请求，从主存储器预读取数据到L2高速缓存中。 预取单元包括：L2高速缓存管理表，其包括以L2缓存的数据存储为单位的每个位置保持存储状态的区域以及保留预取请求的区域; 以及预取控制单元，其指示L2高速缓存从所述处理器核心执行预取请求或预取请求。

公开(公告)号：US20070124523A1

公开(公告)日：2007-05-31

申请号：US11357088

申请日：2006-02-21

申请人： Masaaki Shimizu ,  Naonobu Sukegawa

发明人： Masaaki Shimizu ,  Naonobu Sukegawa

IPC分类号： G06F13/24

CPC分类号： G06F13/24

摘要： Interrupt process generated in a processor for arithmetic operation is offloaded onto a system control processor, thereby reducing disturbance to the processor for arithmetic operation. A heterogeneous multiprocessor system includes: means which accepts an interrupt in each CPU; means which inquires the accepted interrupt of an interrupt destination management table to select an interrupt destination CPU; means which queues the accepted interrupt; means which generates an inter-CPU interrupt to the selected interrupt destination CPU; each means which receives the inter-CPU interrupt in the interrupt source CPU, performs interrupt process of the interrupt source CPU, and generates the inter-CPU interrupt to the interrupt source CPU in the interrupt destination CPU; means which performs an interrupt end process; and means which performs interrupt process in its own CPU when the interrupt destination CPU selected as a result of the inquiry to the interrupt destination management table is its own CPU.

摘要翻译： 在用于算术运算的处理器中产生的中断处理被卸载到系统控制处理器上，从而减少对处理器的干扰以进行算术运算。 异构多处理器系统包括：在每个CPU中接受中断的装置; 查询中断目的地管理表的接受中断以选择中断目的地CPU的装置; 意味着对接受的中断进行排队; 为所选择的中断目标CPU产生CPU间中断的装置; 在中断源CPU中接收到CPU间中断的各种方式，执行中断源CPU的中断处理，并在中断目标CPU中产生中断源CPU中断CPU中断; 执行中断结束过程的手段; 以及当作为对中断目的地管理表的查询结果而选择的中断目的地CPU是其自己的CPU时，在其自己的CPU中执行中断处理的装置。

公开(公告)号：US06466988B1

公开(公告)日：2002-10-15

申请号：US09473276

申请日：1999-12-28

申请人： Naonobu Sukegawa ,  Kouki Uwano ,  Shigeko Hashimoto ,  Masakazu Fukagawa ,  Eiki Kamada

发明人： Naonobu Sukegawa ,  Kouki Uwano ,  Shigeko Hashimoto ,  Masakazu Fukagawa ,  Eiki Kamada

IPC分类号： G06F1300

CPC分类号： G06F12/0815 ,  G06F12/0822

摘要： A shared main memory type multiprocessor is arranged to have a switch connection type. The multiprocessor prepares an instruction for outputting a synchronization transaction. When each CPU executes this instruction, after all the transactions of the preceding instructions are output, the synchronization transaction is output to the main memory and the coherence controller. By the synchronization transaction, the main memory serializes the memory accesses and the coherence controller guarantees the completion of the cache coherence control. This makes it possible to serialize the memory accesses and guarantee the completion of the cache coherence control at the same time.

摘要翻译： 共享的主存储器型多处理器被布置成具有开关连接类型。 多处理器准备用于输出同步事务的指令。 当每个CPU执行该指令时，在输出上述指令的所有事务之后，将同步事务输出到主存储器和相干控制器。 通过同步事务，主存储器将存储器访问序列化，并且相干控制器保证高速缓存一致性控制的完成。 这使得可以同时序列化存储器访问并保证高速缓存一致性控制的完成。

公开(公告)号：US06335903B2

公开(公告)日：2002-01-01

申请号：US09778785

申请日：2001-02-08

申请人： Tetsuhito Nakamura ,  Naonobu Sukegawa ,  Tsuguo Matsuura ,  Masanao Ito

发明人： Tetsuhito Nakamura ,  Naonobu Sukegawa ,  Tsuguo Matsuura ,  Masanao Ito

IPC分类号： G11C800

CPC分类号： G06F13/1631 ,  G06F12/0215

摘要： A memory system having a DRAM or synchronous DRAM as a memory unit. A memory controller which controls the memory unit in correspondence with a memory access request received from a memory access request generator, has a row address buffer for storing a row address extracted from an issued memory access request, avoiding registration of same row address into different positions, a pointer register for storing a pointer to a registration entry in the row address buffer holding the row address, correspondence detection circuit that detects whether or not row addresses of issued access requests correspond with each other by comparing stored pointers, and a memory unit control circuit which continuously issues column addresses of plural requests with row addresses corresponding with each other to the DRAM.

摘要翻译： 具有DRAM或同步DRAM作为存储单元的存储器系统。 存储器控制器，其与从存储器访问请求生成器接收的存储器访问请求相对应地控制存储器单元，具有用于存储从发布的存储器访问请求中提取的行地址的行地址缓冲器，避免将相同行地址注册到不同的位置 用于存储指向存储行地址的行地址缓冲器中的注册条目的指针寄存器，对应检测电路，通过比较存储的指针来检测发出的访问请求的行地址是否相互对应;存储器单元控制 电路，其连续地向DRAM发送具有彼此对应的行地址的多个请求的列地址。