公开(公告)号：US06295579B1

公开(公告)日：2001-09-25

申请号：US09070851

申请日：1998-05-01

申请人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

发明人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

IPC分类号： G06F1200

CPC分类号： G06F12/0813 ,  G06F12/0848 ,  G06F2212/272

摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

摘要翻译： 并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。 并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。 每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

公开(公告)号：US5778429A

公开(公告)日：1998-07-07

申请号：US497751

申请日：1995-07-03

申请人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

发明人： Naonobu Sukegawa ,  Tshiaki Tarui ,  Hiroaki Fujii ,  Hideya Akashi

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0813 ,  G06F12/0848 ,  G06F2212/272

摘要： A parallel processor system controls access to a distributed shared memory and to plural cache memories to prevent frequently-used local data from being flushed out of a cache memory. The parallel processor system includes a plurality of nodes each including a processor and a shared memory in a distributed shared memory arrangement, and a local-remote divided cache memory system, wherein local data and remote data are controlled separately. Each local-remote divided cache memory system includes a local data area, a remote data area, and a cache memory controller by which either the local data area or the remote data area is accessed according to the contents of an access request.

摘要翻译： 并行处理器系统控制对分布式共享存储器和多个高速缓冲存储器的访问，以防止频繁使用的本地数据被从高速缓冲存储器中冲出。 并行处理器系统包括多个节点，每个节点包括分布式共享存储器布置中的处理器和共享存储器，以及本地远程分割高速缓存存储器系统，其中本地数据和远程数据被单独控制。 每个本地远程分割高速缓冲存储器系统包括根据访问请求的内容访问本地数据区域或远程数据区域的本地数据区域，远程数据区域和高速缓存存储器控制器。

公开(公告)号：US6119150A

公开(公告)日：2000-09-12

申请号：US789184

申请日：1997-01-24

申请人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

发明人： Hiroaki Fujii ,  Tadaaki Isobe ,  Makoto Koga ,  Hideya Akashi

IPC分类号： G06F15/17 ,  G06F12/08 ,  G06F15/167 ,  G06F13/00

CPC分类号： G06F12/0837 ,  G06F12/0813

摘要： An instruction processor is employed which performs a cache coherence control according to a request from the storage controller. The storage controller is provided with a cache coherence control processing circuit, which performs the cache coherence control for the addresses which are the destinations of main memory accesses occurring with a data transfer. At the same time, the cache coherence control processing circuit performs the cache coherence control processing once for each cache line in the process of data transfer. The cache coherence control processing performed by software in connection with data transfer is obviated, improving the data transfer efficiency including the cache memory control and reducing limitations on program.

摘要翻译： 采用根据来自存储控制器的请求执行高速缓存一致性控制的指令处理器。 存储控制器设置有高速缓存一致性控制处理电路，其对作为通过数据传送发生的主存储器访问的目的地的地址执行高速缓存一致性控制。 同时，高速缓存一致性控制处理电路在数据传送过程中对每条高速缓存线执行一次高速缓存一致性控制处理。 消除了与数据传输有关的软件执行的高速缓存一致性控制处理，提高了包括缓存存储器控制在内的数据传输效率，并减少了对程序的限制。

公开(公告)号：US06606688B1

公开(公告)日：2003-08-12

申请号：US09642002

申请日：2000-08-21

申请人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

发明人： Masaru Koyanagi ,  Disuke Yamane ,  Hideya Akashi ,  Yuji Tsushima ,  Tadayuki Sakakibara

IPC分类号： G06F1200

CPC分类号： G06F12/0862

摘要： A cache controller stores pre-set variables for pre-fetch block size and stride value. A cache controller receives an access request for the main memory from the processor, and generates a pre-fetch request based an the access request and the variables. The cache controller reads data from main memory based on the generated pre-fetch request and writes this data to the cache memory.

摘要翻译： 缓存控制器存储用于预取块大小和步幅值的预设变量。 缓存控制器从处理器接收对主存储器的访问请求，并且基于访问请求和变量生成预取请求。 高速缓存控制器基于生成的预取请求从主存储器读取数据，并将该数据写入缓存存储器。

公开(公告)号：US06591325B1

公开(公告)日：2003-07-08

申请号：US09547392

申请日：2000-04-11

申请人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Yuji Tsushima ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1314

CPC分类号： G06F13/4204

摘要： An information processing system that transfers transactions between a plurality of system modules. A request side interface unit in a request side module has a request ID queue in which issued request transactions are stored in order of issuance. A request side queue pointer points to an entry in this request ID queue corresponding to a response transaction to be accepted next. A response side interface unit in a response side module has a response queue in which accepted request transactions are stored in order of acceptance. A response side queue pointer points to an entry in this response queue corresponding to a response transaction to be issued next. Therefore, a request transaction and the corresponding response transaction are transferred between the request side interface unit and the response side interface unit without transferring transaction IDs. When the response order is changed, the response side interface unit issues a command, which changes the value of the request side queue pointer, to inform the request side interface unit of the change in the order.

摘要翻译： 一种在多个系统模块之间传送交易的信息处理系统。 请求侧模块中的请求侧接口单元具有请求ID队列，其中发出的请求事务按照发布的顺序存储。 请求侧队列指针指向与要接受的响应事务相对应的该请求ID队列中的条目。 响应侧模块中的响应侧接口单元具有响应队列，其中接受请求事务按接受顺序存储。 响应侧队列指针指向对应于接下来要发出的响应事务的该响应队列中的条目。 因此，在请求侧接口单元和响应侧接口单元之间传送请求事务和相应的响应事务，而不转移事务ID。 当响应顺序改变时，响应侧接口单元发出改变请求侧队列指针的值的命令，以通知请求侧接口单元的顺序改变。

公开(公告)号：US06438653B1

公开(公告)日：2002-08-20

申请号：US09330981

申请日：1999-06-14

申请人： Hideya Akashi ,  Toshio Okochi ,  Toru Shonai ,  Masamori Kashiyama

发明人： Hideya Akashi ,  Toshio Okochi ,  Toru Shonai ,  Masamori Kashiyama

IPC分类号： G06F1206

CPC分类号： G06F12/0831 ,  G06F12/0864

摘要： A multi-processor system includes a plurality of processor node control circuits in respective processor nodes, and a cache memory which is an external cache. Each of the processor node control circuits includes a summarized cache tag memory for storing “summarized information” which is information having a reduced number of bits by summarizing information on a cache tag portion in the cache memory and indicating whether each of blocks is effectively indexed in the cache tag portion. For cache coherence control, the summarized cache tag memory is first accessed, so that the cache tag portion is accessed only when it is determined that a target block is effectively indexed, to determine whether the cache coherence control for the node is required.

摘要翻译： 多处理器系统包括在各个处理器节点中的多个处理器节点控制电路和作为外部高速缓存的高速缓存存储器。 每个处理器节点控制电路包括总结高速缓存标签存储器，用于通过汇总高速缓冲存储器中的高速缓存标签部分上的信息并指示每个块是否被有效地索引到存储器中来存储具有减少位数的信息的“汇总信息” 缓存标签部分。 对于高速缓存一致性控制，首先访问汇总的高速缓存标签存储器，使得只有在确定目标块被有效地索引时才能访问高速缓存标签部分，以确定是否需要该节点的高速缓存一致性控制。

公开(公告)号：US6088770A

公开(公告)日：2000-07-11

申请号：US30957

申请日：1998-02-26

申请人： Toshiaki Tarui ,  Koichi Okazawa ,  Yasuyuki Okada ,  Toru Shonai ,  Toshio Okochi ,  Hideya Akashi

发明人： Toshiaki Tarui ,  Koichi Okazawa ,  Yasuyuki Okada ,  Toru Shonai ,  Toshio Okochi ,  Hideya Akashi

IPC分类号： G06F15/177 ,  G06F12/02 ,  G06F12/08 ,  G06F15/17 ,  G06F13/14

CPC分类号： G06F12/0826 ,  G06F12/0284 ,  G06F2212/2542

摘要： A shared memory multiprocessor (SMP) has efficient access to a main memory included in a particular node and a management of partitions that include the nodes. In correspondence with each page of main memory included in a node, a bit stored in a register indicates if the page has been accessed from any other node. In a case where the bit is "0", a cache coherent command to be sent to the other nodes is not transmitted. The bit is reset by software at the time of initialization and memory allocation, and it is set by hardware when the page of the main memory is accessed from any other node. In a case where the interior of an SMP is divided into partitions, the main memory of each node is divided into local and shared areas, for which respectively separate addresses can be designated. In each node, the configuration information items of the shared area and the local area are stored in registers. The command of access to the shared area is multicast to all of the nodes, whereas the command is multicast only to the nodes within the corresponding partition when the local area is accessed.

公开(公告)号：US06993633B1

公开(公告)日：2006-01-31

申请号：US09628718

申请日：2000-07-28

申请人： Tadayuki Sakakibara ,  Isao Ohara ,  Hideya Akashi ,  Yuji Tsushima ,  Satoshi Muraoka

发明人： Tadayuki Sakakibara ,  Isao Ohara ,  Hideya Akashi ,  Yuji Tsushima ,  Satoshi Muraoka

IPC分类号： G06F9/38

CPC分类号： G06F12/0862 ,  G06F12/084

摘要： A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.

摘要翻译： 一种用于计算机系统的高速缓存数据控制系统和方法，其中在存储器读取处理中，相干控制器在读取之前向高速缓存数据控制器发送用于（推测性地）将数据从高速缓存数据部分读取的高级推测性读请求 缓存标签从缓存标签部分进行缓存命中检查。 如果发生了高速缓存命中，则高速缓存数据控制器接收到由相干控制器发出的读请求时，将经过推测读取的数据作为响应数据返回。

公开(公告)号：US06389518B1

公开(公告)日：2002-05-14

申请号：US09523737

申请日：2000-03-13

申请人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

发明人： Yuji Tsushima ,  Hideya Akashi ,  Keitaro Uehara ,  Naoki Hamanaka ,  Toru Shonai ,  Tetsuhiko Okada ,  Masamori Kashiyama

IPC分类号： G06F1200

摘要： In a multiprocessor arranged in accordance with either NUMA or UMA in which a plurality of processor nodes containing a plurality of processor units are coupled to each other via a network, a cache snoop operation executed in connection with a memory access operation is performed at two stages, namely, local snoop operation executed within a node, and global snoop operation among nodes. Before executing the local snoop operation, an ACTV command for specifying only an RAS of a memory is issued to a target node having a memory to be accessed, and the memory access is activated in advance. A CAS of a memory is additionally specified and a memory access is newly executed after the ACTV command has been issued and then a memory access command has been issued. When there is such a possibility that a memory to be accessed is cached in a processor node except for a source node, this memory access command is issued to be distributed to all nodes so as to execute the global snoop operation. On the other hand, when there is no possibility that the memory to be accessed is cached, this memory access command is transferred only to the target node in yan one-to-one correspondence.

公开(公告)号：US06839806B2

公开(公告)日：2005-01-04

申请号：US09941696

申请日：2001-08-30

申请人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

发明人： Yoshiki Murakami ,  Masaru Koyanagi ,  Hideya Akashi

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0855 ,  G06F12/0831

摘要： A cache system comprising a cache tag buffer 270 for storing a part of a cache tag memory 260. When a memory processing request is issued from a processor 10, a cache control means 280 retrieves both of the cache tag memory 260 and the cache tag buffer 270. If a target cache block is present in the cache tag buffer 270, then, without waiting for a retrieval result of the cache tag memory 260, the cache control circuit 280 accesses the cache data memory 250 using information of the cache block.